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Minimum Energy CMOS Design with Dual Subthrehold Supply and Multiple Logic-Level Gates Kyungseok Kim and Vishwani D. Agrawal ECE Dept. Auburn University.

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Presentation on theme: "Minimum Energy CMOS Design with Dual Subthrehold Supply and Multiple Logic-Level Gates Kyungseok Kim and Vishwani D. Agrawal ECE Dept. Auburn University."— Presentation transcript:

1 Minimum Energy CMOS Design with Dual Subthrehold Supply and Multiple Logic-Level Gates Kyungseok Kim and Vishwani D. Agrawal ECE Dept. Auburn University Auburn, AL 36849, USA ISQED 2011, Santa Clara, CA, USA March 16, 2011

2 Subthreshold Circuits March 16ISQED 20112 V dd < V th E min Low to Medium Speed Micro-sensor networks, Pacemakers, RFID tags, and Portable devices

3 Motivation March 16ISQED 20113  Energy budget is more stringent for long battery life.  Minimum energy operation has a huge penalty in system performance, limiting its applications to niche market.  Utilizing time slack for low power design is common at above-threshold, but has not been explored in subthreshold regime.  Sizing affects functional failure [1] and multi-V th may not be adequate to utilize time slack in subthreshold region [2].  Two supply voltages are manageable and acceptable in modern VLSI systems.

4 32-bit Ripple Carry Adder* March 16ISQED 20114 0.67X 7.17X * SPICE Simulation of PTM 90nm CMOS

5 Low Power Design Using Dual-V dd March 16ISQED 20115 CVS Structure [3] ECVS Structure [4] FF FF/LCFF LCFF FF/LCFF VDDHVDDL

6 Multiple Logic-Level Gates (Delay) March 16ISQED 20116 Multiple Logic-Level NAND2 [5] DCVS PG ** Optimized Delay by Sizing with HSPICE with HSPICE ** SPICE Simulation for PTM 90nm CMOS

7 Multiple Logic-Level Gates (P leak ) March 16ISQED 20117 ** SPICE Simulation for PTM 90nm CMOS V dd = 300mV Normalized to a standard INV with V dd = V in = 300mV

8 MILP for Minimum Energy Design Objective Function: **Integer variable X i,v and P i,v March 16ISQED 20118 Total Energy per cycle Leakage energy penalty from multiple logic-level gates

9 Timing Constraints March 16ISQED 20119 Delay penalty from multiple logic-level gates T i is the latest arrival time at the output of gate i from PI events

10 Penalty Constraints March 16ISQED 201110 Boolean AND Boolean OR

11 Dual Supply Voltages Selection March 16ISQED 201111 Bin-packing [6]

12 ISCAS’85 Benchmark ** PTM 90nm CMOS March 16ISQED 201112

13 Total Energy Saving (%) March 16ISQED 201113

14 Gate Slack Distribution c7552 March 16ISQED 201114 c880 c5315 c6288 Optimized Optimized Optimized Optimized

15 Conclusion & Future Work  Dual V dd design is valid for energy reduction below the minimum energy point in a single V dd as well as for substantial speed-up within tight energy budget of a bulk CMOS subthreshold circuit.  Use of a conventional level converter is not affordable by huge delay penalty for dual-V dd design in subthreshold regime.  Delay of a subthreshold circuit is susceptible to process variation and accounting for that aspect is needed.  Runtime of MILP is too expensive and gate slack analysis can reduce the exponential time complexity of MILP to linear. March 16ISQED 201115

16 [1] A.Wang, B. H. Calhoun, and A. P. Chandrakasan, Sub-Threshold Design for Ultra Low-Power Systems. Springer, 2006.. [2] D. Bol, D. Flandre, and J.-D. Legat, “Technology Flavor Selection and Adaptive Techniques for Timing-Constrained 45nm Subthreshold Circuits,” in Proceedings of the 14th ACM/IEEE International Symposium on Low Power Electronics and Design, 2009, pp. 21–26. [3]K. Usami and M. Horowitz, “Clustered Voltage Scaling Technique for Low-Power Design,” in Proc. International Symposium on Low Power Design, 1995, pp. 3–8. [4]K. Usami, M. Igarashi, F. Minami, T. Ishikawa, M. Kanzawa,M. Ichida, and K. Nogami, “Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor,” IEEE Journal of Solid-State Circuits, vol. 33, no. 3, pp. 463–472, 1998. [5] A. U. Diril, Y. S. Dhillon, A. Chatterjee, and A. D. Singh, “Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages,” IEEE Trans. on VLSI Systems, vol. 13, no. 9, pp. 1103–1107, Sept. 2005. [6] M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, “Dynamic and Leakage Power Reduction in MTCMOS Circuits using an Automated Efficient Gate Clustering Technique,” in Proc. 39 th Design Automation Conf., 2002, pp. 480–485. [7]K. Kim and V. D. Agrawal, “True Minimum Energy Design Using Dual Below- Threshold Supply Voltages,” in Proc. 24th International Conference on VLSI Design, Jan. 2011.References March 16ISQED 201116

17 March 16ISQED 201117

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