Presentation on theme: "Each of layers have their own characteristics like capacitance and resistances Concepts such as sheet resistance Rs and a standard unit capacitance □Cg."— Presentation transcript:
Each of layers have their own characteristics like capacitance and resistances Concepts such as sheet resistance Rs and a standard unit capacitance □Cg Also delay associated with wiring, with inverters and with other circuitry may be evaluated in terms of a delay unit τ.
Consider a uniform slab of conduction material of resistivity ρ,of width W, thickness t, length between faces L Consider the resistance between two opposite faces R AB = ρL/A Ω Where area of the slab A=Wt. R AB = ρL/Wt Ω
Now, consider the case in witch L=W, that is a square of resistive material, then R AB = ρ/t =R s Where R s =ohm per square or sheet resistance The table of values for a 5µm technology is listed below.5µm technology means minimum line width is 5µm and λ= 2.5µm.
Estimation of CMOS inverter delay The inverter either charges or discharges the load capacitance CL. Raise-time and fall-time estimations obtained by following analysis
In this condition p-device stays in saturation for entire charging period of the load capacitance C L the p device is in saturation current given by I dsp =ßp(V gs -|V tp |) 2 / 2 ----(1)
The above current charges the capacitance and it has a constant value. The output is the drop across the capacitance, given by Vout =I dsp x t / C L ------(2) Let t= τ r,Vout=Vdd, Vtp=0.2Vdd and Vgs=Vdd We have τ r = 3C L /ßpV dd
Fall time estimation Similar reasoning can be applied to the discharge of CL through the n- transistor Making similar assumptions we may write for fall- time : τ f = 3C L /ßnV dd
Summary of CMOS fall time and rise factors Final expression we may deduce that: τ r / τ f = ßn / ßp Raise time is slower by factor of 2.5 when both ‘n’ and ‘p’ are in same size In order to achive symmetrical operation need to make Wp=2.5 Wn The factors which affect rise-time and fall-time as follows: 1)τ r and τ f are proportional to 1/Vdd 2)τ r and τ f are proportional to CL 3)τ r =2.5 τ f for equal n and p transistor geometries
The problem of driving large capacitive loads arises when signals must travel outside the chip. Usually it so happens that the capacitance outside the chip are higher. To reduce the delay these loads must be driven by low resistance.
Super buffers are better solution for large capacitance load delay problems Consider Vin=1 Inverter formed by T1 and T2 is turned on and thus the gate of T3 is pulled down to 0V but T4 is turned on and the output is pulled down Consider Vin=0,then the gate of T3 is allowed to rise quickly to Vdd,T4 is turned off. T3 is made to conduct with Vdd on its gate,i.e twice the average voltage that applied to gate
High current drive capabilities for small areas in silicon Working of bipolar transistor depends on two main timing components: 1)T in the time required to charge the base of the transistor which is large 2)T L the time take to charge output load capacitor which is less BiCMOS driver
Delay T Load Capacitance C L Tin C L (crit) CMOS BiCMOS Critical value of load capacitance CL(crit) below which the BiCMOS driver is slower than a comparable CMOS driver
Cascaded inverters as drivers N cascaded inverters, each one of which is larger than the preceding by a width factor f. Now both f and N can be complementary. If f for each stage is large the number of stages N reduces but delay per stage increases. Therefore it becomes essential to optimize. CLCL GND 4:1 1:1 4: f 1: f 4: f 2 1: f 2
Fix N and find the minimum value of f. For nMOS inverters Delay per stage = fτ for ↑Vin or = 4fτ for ↓Vin The delay for a nMOS pair is 5 fτ
For N=even Td=2.5 Neτ for nmos, Td=3.5 Neτ for cmos For N=odd Transition from 0 to 1 Transition from1 to 0 nMOSTd=[2.5(N-1)+1] eτTd=[2.5(N-1)+4]eτ CMOSTd=[3.59N-1)+2]eτTd=[3.5(N-1)+5]eτ
Propagation delay Cascaded pass transistors: delay introduced when the logic signals have to pass through a chain of pass transistors The transistors could pose a RC product delay Ex: the response at node V2 is given by C dV 2 /dt =(I 1 -I 2 )= [(V 1 -V 2 )(V 2 -V 3 )]/R
Lump all the R and C we have R total =nrRs ….eq-1 C total =nc ﾛ Cg ….eq-2 Where r=relative resistance/section in terms of Rs c=relative capacitance/section in terms of ﾛ Cg Overall delay τd for n sections is given by τ d = n 2 rc Long wires may be a problem with slowly rising signals
wiring capacitances Fringing field: is due to parallel fine metal lines running across the chip for power connection. Total wire capacitance Cw=Carea+Cff Interlayer capacitance: is due to different layers cross silicon area Peripheral capacitance: is due to junction of two devices (regions) Total diffusion capacitance Ctotal = Carea + Cperi
Choice of layer 1)Vdd and Vss lines must be distributed on metal lines due to low Rs value 2)Long lengths of poly must be avoided because they have large Rs 3)The resistance effects of the transistors are much larger, hence wiring effects due to voltage divider effects b/w wiring and transistor resistances 4)Diffusion areas must be carefully handled because they have larger capacitance to substrate.