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**Static CMOS Gates Jack Ou, Ph.D.**

Lecture 5 Static CMOS Gates Jack Ou, Ph.D.

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**2-Input NOR Gate F can only be pulled up if A=B=0 V**

F can be pulled down by either A=1 or B=1. (Or Both)

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**2-Input NAND Gate F can only be pulled down if both A=B=1.**

F will be pulled up if either A or B is 0 V.

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NAND Gates

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NOR Gates

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2-Input AND Gate NAND

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2-Input OR Gate NOR

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**Alternative Implementation for High Fanin Gates**

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**Steps for Generating Non-Trivial Static CMOS Logic Circuits**

1. Implement the pull-down (NMOS)circuit using 𝐹 Useful technique: DeMorgan’s Theorem Synthesize the dual of the pull-down circuits using PMOS

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**DeMorgan’s Theorem The complement of a function can be obtained by**

Replacing each variable with its complement Exchange the AND and OR functions Example 𝐴+𝐵 𝐶 = 𝐴+𝐵 + 𝐶 = 𝐴 𝐵 + 𝐶

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Dual The dual of any logic function can be obtained by exchanging the AND and OR operations. ab ↔a+b (a+b)c ↔ab+c

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**A fictional AND Circuit**

The current flows only when both A and B are closed.

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Fictional OR Circuit The current flows when either A or B is closed.

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Implementation Use transistors in series to implement a logical AND function Use transistors in parallel to implement a logical OR function

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OAI Circuit ( 𝐴+𝐵 𝐶 )

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XOR/XNOR

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Mux

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**Determine a Boolean Expression a Schematic**

Determine 𝐹 implemented by a NMOS pull-down network. Complement 𝐹 to obtain F.

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2-Input XOR XNOR 𝐴0𝐴1 (A0+A1 𝐴0𝐴1 (A0+A1) 𝐴0 𝐴1 𝐴0+𝐴1 𝐴0𝐴1

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CMOS Gate Sizing

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Device Sizing Obtain the same delay as the inverter for the rise/fall cases. ReffN=12.5 Kohm/SQ, ReffP=30 Kohm/SQ Reff=Reff(L/W) ReffP/ReffN=2.4 To achieve the same delay, (assume LP=LN, WP=2.4WN, WP/WN is approximately 2.

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**Size Devices for the Worst Case**

Series transistors: Increase W to reduce Reff. Parallel transistors: assume the worst case, i.e. only one of the parallel transistor is ON.

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**Transistor Sizing Without Velocity Saturation**

Figure 5.2 Assumption: Equal rise delay and fall delay Consideration: Effective Resistance

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Inverter

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Inverter tPHL tPHL= pS

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NAND2 Test Circuit

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NAND2 tPHL tPHL=66.01 pS

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**Effective Width Transistors in Series Transistors in Parallel**

W1||W2||W3 Transistors in Parallel W+W2+W3

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**Trade-Off Increase W to reduce the effective**

Resistance for the pull down network. The area is increased.

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**FO4 Fanout ratio: total capacitance driven by a gate dividing**

by its input capacitance

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VTC of Gates

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**Adjust VS Knob: χ as defined in EQ. 4.15**

Increase WNLP/LNWP to decreased VS. Decrease WNLP/LNWP to increased VS.

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**Switching Voltage of a NAND Gate**

Both inputs tied together: effective WN=W, WP=4W, VS shifts to the right. Both input A=high, sweep VB: effective WN=2W, WP=2W, VS shifts to the left.

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**Switching Voltage of a NOR Gate**

Both inputs tied together: effective WN=2W, WP=2W, VS shifts to the left. Both input A=ground, sweep VB: effective WN=W, WP=4W, VS shifts to the right.

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1 ECE2030 Introduction to Computer Engineering Lecture 4: CMOS Network Prof. Hsien-Hsin Sean Lee School of ECE Georgia Institute of Technology.

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