Presentation on theme: "Lecture 5 Static CMOS Gates Jack Ou, Ph.D.. 2-Input NOR Gate F can only be pulled up if A=B=0 V F can be pulled down by either A=1 or B=1. (Or Both)"— Presentation transcript:
Lecture 5 Static CMOS Gates Jack Ou, Ph.D.
2-Input NOR Gate F can only be pulled up if A=B=0 V F can be pulled down by either A=1 or B=1. (Or Both)
2-Input NAND Gate F can only be pulled down if both A=B=1. F will be pulled up if either A or B is 0 V.
2-Input AND Gate NAND
2-Input OR Gate NOR
Alternative Implementation for High Fanin Gates
Steps for Generating Non-Trivial Static CMOS Logic Circuits
Dual The dual of any logic function can be obtained by exchanging the AND and OR operations. – ab a+b – (a+b)c ab+c
A fictional AND Circuit The current flows only when both A and B are closed.
Fictional OR Circuit The current flows when either A or B is closed.
Implementation Use transistors in series to implement a logical AND function Use transistors in parallel to implement a logical OR function
Determine a Boolean Expression a Schematic
2-Input XOR XNOR
CMOS Gate Sizing
Device Sizing Obtain the same delay as the inverter for the rise/fall cases. – R effN =12.5 Kohm/SQ, R effP =30 Kohm/SQ – R eff =R eff (L/W) – R effP /R effN =2.4 – To achieve the same delay, (assume L P =L N, W P =2.4W N, W P /W N is approximately 2.
Size Devices for the Worst Case Series transistors: Increase W to reduce R eff. Parallel transistors: assume the worst case, i.e. only one of the parallel transistor is ON.
Transistor Sizing Without Velocity Saturation Figure 5.2 Assumption: Equal rise delay and fall delay Consideration: Effective Resistance
Inverter t PHL tPHL= pS
NAND2 Test Circuit
NAND2 t PHL tPHL=66.01 pS
Effective Width Transistors in Series – W1||W2||W3 Transistors in Parallel – W+W2+W3
Trade-Off Increase W to reduce the effective Resistance for the pull down network. The area is increased.
FO4 Fanout ratio: total capacitance driven by a gate dividing by its input capacitance
VTC of Gates
Adjust V S Knob: – χ as defined in EQ – Increase W N L P /L N W P to decreased V S. – Decrease W N L P /L N W P to increased V S.
Switching Voltage of a NAND Gate Both inputs tied together: effective W N =W, W P =4W, VS shifts to the right. Both input A=high, sweep VB: effective W N =2W, W P =2W, VS shifts to the left.
Switching Voltage of a NOR Gate Both inputs tied together: effective W N =2W, W P =2W, VS shifts to the left. Both input A=ground, sweep VB: effective W N =W, W P =4W, VS shifts to the right.