1. VLSIVLSI Prof. Vojin G. Oklobdzija References (used for creation of the presentation material): [1] Mead, Conway, “Introduction to VLSI Systems”, Addison Wesley Publishing. [2] Glasser, Dobberpuhl, “The Design and Analysis of VLSI Circuits”, Addison Wesley Publishing. [3] Weste, Eshraghian, “Principles of CMOS VLSI Design”, Addison Wesley Publishing. [4] Shoji, “CMOS Digital Circuits Technology”, Prentice Hall.

2. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design2 Historical Overview nMOS era: 1970-85 Pass-transistor design CMOS existed early but took off 1985 on Domino CMOS, 1982 –NORA –DCVSL CPL, DPL –DCVS-PG –SRPL –LEAP SOI-CMOS

3. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design3 n-MOS Design Era 1970-85 LSI started with nMOS: pass-transistor design experience: -Flourished at the beginning of the nMOS era (popularized by Mead-Conway book) -Allows high density layout and compact design style -Fast: outperforming gate based design -Low in power Drawbacks: –Not compatible with existing design tools –Exhibiting testability and reliability problems

4. Review of CMOS Prof. Vojin G. Oklobdzija

5. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design5 CMOS Basics

6. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design6 CMOS Basics

7. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design7 CMOS Basics

8. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design8 CMOS Basics A complex path example:

9. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design9 CMOS Basics More complex blocks are realizable in CMOS Primitive gates:

10. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design10 CMOS Deficiencies: Muli-Input NOR function in CMOS is slow Various remedies:

11. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design11 CMOS Deficiencies and Remedies

12. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design12 CMOS Deficiencies and Remedies

13. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design13 CMOS Basic Inverter Transfer function: Logic voltage levels are V OH and V OL and V IL and V IH The inverter transfer function lie within the shaded region

14. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design14 CMOS Basic: Inverter Characteristic LeakageCurrents

15. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design15 CMOS Basic: Inverter Characteristic

16. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design16 CMOS Basic: Inverter Characteristic Transistors during the transition

17. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design17 CMOS Basic: Inverter Switching

18. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design18 CMOS Basic: Power During the static state there is no currentDuring the static state there is no current Current is only present during transistion:Current is only present during transistion: -Short circuit current (crow-bar current) -Charging and discharging of the output capacitor -Leakage Current

19. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design19 CMOS Basic: Power This is an E=mc 2 of low-power design There are three ways to control power: -Reducing Power-Supply Voltage (most effective !!) -Reducing the switching activity k (various ways) -Reducing C L (technology scaling etc.) -Reducing the required frequency of operation (?) P CMOS =kC L V 2 DD f o

20. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design20 CMOS Basic: Delay Which one of the three designs is the fastest ? How can we find this out without simulation ? Learn about Logical Effort !

21. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design21 CMOS Basic: Delay

22. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design22 CMOS Basic: Delay Delay can be approximated with: R ND7 C in1 +R NOR C in2 +R ND2 C out

23. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design23 CMOS Basic: Delay Delay of a signal path in CMOS logic is dependent on: Fan-in of a gate –Represented as a resistance of the pull- up/down transistor path of the gate Fan-out of a gate –Represented as a capacitive load at the output Number of CMOS blocks in the path. Wire delay connecting various blocks.

24. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design24 CMOS Basic: Delay Delay of a signal path in CMOS logic can be reduced by: Making the transistors larger in order to minimize resistance of a pull-up/down path in the gate Making the transistors smaller in order to minimize the capacitive load of each gate Reducing the number of CMOS blocks in the path. Bringing the blocks closer and/or choosing the less wire intensive topology. –Note that these requirements are often contradictory

25. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design25 CMOS Basic: Delay How to estimate delay and critical timing in CMOS circuits ? How to determine the proper transistor sizing in order to make a compromise with contradicting requirements ? How to choose the right circuit topology ? The Answer: “Logical Effort”

26. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design26 Pass-Transistor Design

27. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design27 Pass-Transistor Design Another way of looking at Karnaugh Map: AND function

28. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design28 Pass-Transistor Design Two-variable function

29. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design29 Pass-Transistor Design “Threshold Voltage Drop” problem:

30. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design30 Pass-Transistor Design Solving the “Threshold Voltage Drop” problem in CMOS:

31. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design31 Pass-Transistor Design Function Generator

32. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design32 Pass-Transistor Design Full 1-bit Adder

33. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design33 Pass-Transistor Design Compact ALU Example (IBM PC/RT) Circ. 1984

34. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design34 Control LinesOutput Control A - inputsB - inputs OddEvenOddEven OperationK1K2QnAABBOddEven Arithmetic A+BAdd0000110011001 A+B+10010110011001 A-BSubtract0010110100101 B-ASubtract0011001011001 B+1Increment0011100011001 +12s compl0011100100101 A+1Increment0010110110001 +12s compl0011001110001 Logical 11100000000000 B1100000010100 1100000101000 1100101010100 1100101101000 1101010000000 1101010010100 01100000000011 1101010101011 A1101010000011 1100101010111 1100101101011 1101010010111 0100101010111 0100101101011 0101010010111

35. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design35 Pass-Transistor Design Compact ALU Example (IBM PC/RT)

36. Fall 2004Prof. V.G. Oklobdzija: High-Performance System Design36 Using Pass-Transistor Design to Speed- up Addition