1. S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. S. Reda EN160 SP’07 Power and Energy Power is drawn from a voltage source attached to the V DD pin(s) of a chip. Instantaneous Power: Energy: Average Power:

3. S. Reda EN160 SP’07 Dynamic power Dynamic power is required to charge and discharge load capacitances when transistors switch. One cycle involves a rising and falling output. On rising output, charge Q = CV DD is required On falling output, charge is dumped to GND This repeats Tf sw times over an interval of T

4. S. Reda EN160 SP’07 Dynamic power dissipation VinVout C L Vdd Energy delivered by the supply during input 1  0 transition: Energy stored at the capacitor at the end of 1  0 transition: dissipated in NMOS during discharge (input: 0  1) load capacitance (gate + diffusion + interconnects)

5. S. Reda EN160 SP’07 Capacitive dynamic power  If the gate is switched on and off f 0  1 (switching factor) times per second, the power consumption is given by  For entire circuit where α i is activity factor [0..0.5] in comparison to the clock frequency (which has switching factor of 1)

6. S. Reda EN160 SP’07 Short circuit current When transistors switch, both nMOS and pMOS networks may be momentarily ON at once Leads to a blip of “short circuit” current. < 10% of dynamic power if rise/fall times are comparable for input and output

7. S. Reda EN160 SP’07 Dynamic power breakup Total dynamic Power [source: Intel’03]

8. S. Reda EN160 SP’07 Calculating dynamic power: An example 200 Mtransistor chip (1.2 V 100 nm process C g = 2 fF/mm) –20M logic transistors Average width: 12 λ –180M memory transistors Average width: 4 λ Static CMOS logic gates: activity factor = 0.1 Memory arrays: activity factor = 0.05 (many banks!) Estimate dynamic power consumption per MHz.

9. S. Reda EN160 SP’07 Static (leakage) power Static power is consumed even when chip is quiescent. –Leakage draws power from nominally OFF devices

10. S. Reda EN160 SP’07 Leakage example The process has two threshold voltages and two oxide thicknesses. Subthreshold leakage: –20 nA/  m for low V t –0.02 nA/  m for high V t Gate leakage: –3 nA/  m for thin oxide –0.002 nA/  m for thick oxide Memories use low-leakage transistors everywhere Gates use low-leakage transistors on 80% of logic

11. S. Reda EN160 SP’07 Leakage power (continued) Estimate static power: –High leakage: –Low leakage:  If no low leakage devices, Pstatic = 749 mW (!)

12. S. Reda EN160 SP’07 Techniques for low-power design Reduce dynamic power –  : clock gating, sleep mode –C: small transistors (esp. on clock), short wires –V DD : lowest suitable voltage –f: lowest suitable frequency Enable Clock Clock Gating only reduce supply voltage of non critical gates I1I1 I2I2 I3I3 I4I4 I5I5 I6I6 O1O1 O2O2 critical path

13. S. Reda EN160 SP’07 Dynamic power reduction via dynamic V DD scaling Scaling down supply voltage –reduces dynamic power –reduces saturation current  increases delay  reduce the frequency Dynamic voltage scaling (DVS): Supply and voltage of the circuit should dynamic adjust according to the workload of our circuits and criticality of the tasks

14. S. Reda EN160 SP’07 Reducing static power Reduce static power –Selectively use low V t devices –Leakage reduction: - stacked devices, body bias, low temperature

15. S. Reda EN160 SP’07 Leakage reduction via adjusting of V th Leakage depends exponentially on V th. How to control V th ? –Remember: V th also controls your saturation current  delay 2. Oxide thickness1. Body Bias I1I1 I2I2 I3I3 I4I4 I5I5 I6I6 O1O1 O2O2 critical path Sol1: statically choose high V t cells for non critical gates Sol2: dynamically adjust the bias of the body idle: increase V t (e.g. by applying –ve body bias on NMOS) Active: reduce V t (e.g.: by applying +ve body bias on NMOS)

16. S. Reda EN160 SP’07 Leakage reduction via Cooling  Impact of temperature on leakage current

17. S. Reda EN160 SP’07 Summary We are still in chapter 4: We covered delay and power estimation Next time, we going to move into integrating the impact of wires into delay/power calculations