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Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits1 VLSI Prof. Vojin G. Oklobdzija References (used for creation of the presentation material):

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Presentation on theme: "Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits1 VLSI Prof. Vojin G. Oklobdzija References (used for creation of the presentation material):"— Presentation transcript:

1 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits1 VLSI Prof. Vojin G. Oklobdzija References (used for creation of the presentation material): [1] Mead, Conway, “Introduction to VLSI Systems”, Addison Wesley Publishing. [2] Glasser, Dobberpuhl, “The Design and Analysis of VLSI Circuits”, Addison Wesley Publishing. [3] Weste, Eshraghian, “Principles of CMOS VLSI Design”, Addison Wesley Publishing. [4] Shoji, “CMOS Digital Circuits Technology”, Prentice Hall.

2 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits2 Historical Overview nMOS era: Pass-transistor design Domino CMOS, 1982 –NORA –DCVSL CPL, DPL –DCVS-PG –SRPL –LEAP SOI-CMOS

3 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits3 n-MOS Design Era LSI started with nMOS: pass-transistor design experience: -Flourished at the beginning of the nMOS era (popularized by Mead-Conway book) -Allows high density layout and compact design style -Fast: outperforming gate based design -Low in power Drawbacks: –Not compatible with existing design tools –Exhibiting testability and reliability problems

4 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits4 Pass-Transistor Design Another way of looking at Karnaugh Map: AND function

5 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits5 Pass-Transistor Design Two-variable function

6 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits6 Pass-Transistor Design “Threshold Voltage Drop” problem:

7 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits7 Pass-Transistor Design Solving the “Threshold Voltage Drop” problem in CMOS:

8 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits8 Pass-Transistor Design Function Generator

9 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits9 Pass-Transistor Design Full 1-bit Adder

10 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits10 Pass-Transistor Design Compact ALU Example (IBM PC/RT) Circ. 1984

11 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits11 Control LinesOutput Control A - inputsB - inputs OddEvenOddEven OperationK1K2QnAABBOddEven Arithmetic A+BAdd A+B A-BSubtract B-ASubtract B+1Increment s compl A+1Increment s compl Logical B A

12 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits12 Pass-Transistor Design Compact ALU Example (IBM PC/RT)

13 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits13 Using Pass-Transistor Design to Speed-up Addition

14 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits14 Review of CMOS Prof. Vojin G. Oklobdzija

15 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits15 CMOS Basics

16 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits16 CMOS Basics

17 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits17 CMOS Basics

18 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits18 CMOS Basics A complex path example:

19 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits19 CMOS Basics More complex blocks are realizable in CMOS Primitive gates:

20 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits20 CMOS Deficiencies: Muli-Input NOR function in CMOS is slow Various remedies:

21 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits21 CMOS Deficiencies and Remedies

22 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits22 CMOS Deficiencies and Remedies

23 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits23 CMOS Basic Inverter Transfer function: Logic voltage levels are V OH and V OL and V IL and V IH The inverter transfer function lie within the shaded region

24 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits24 CMOS Basic: Inverter Characteristic

25 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits25 CMOS Basic: Inverter Characteristic

26 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits26 CMOS Basic: Inverter Characteristic Transistors during the transition

27 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits27 CMOS Basic: Inverter Switching

28 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits28 CMOS Basic: Power During the static state there is no current Current is only present during transistion: -Short circuit current (crow-bar current) -Charging and discharging of the output capacitor -Leakage Current

29 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits29 CMOS Basic: Power This is an E=mc 2 of low-power design There are three ways to control power: -Reducing Power-Supply Voltage (most effective !!) -Reducing the switching activity k (various ways) -Reducing C L (technology scaling etc.) -Reducing the required frequency of operation (?) P CMOS =kC L V 2 DD f o

30 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits30 CMOS Basic: Delay Which one of the three designs is the fastest ? How can we find this out without simulation ? Learn about Logical Effort !

31 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits31 CMOS Basic: Delay

32 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits32 CMOS Basic: Delay Delay can be approximated with: R ND7 C in1 +R NOR C in2 +R ND2 C out

33 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits33 CMOS Basic: Delay Delay of a signal path in CMOS logic is dependent on: Fan-in of a gate –Represented as a resistance of the pull-up/down transistor path of the gate Fan-out of a gate –Represented as a capacitive load at the output Number of CMOS blocks in the path. Wire delay connecting various blocks.

34 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits34 CMOS Basic: Delay Delay of a signal path in CMOS logic can be reduced by: Making the transistors larger in order to minimize resistance of a pull-up/down path in the gate Making the transistors smaller in order to minimize the capacitive load of each gate Reducing the number of CMOS blocks in the path. Bringing the blocks closer and/or choosing the less wire intensive topology. –Note that these requirements are often contradictory

35 Prof. V.G. OklobdzijaAdvanced Digital Integrated Circuits35 CMOS Basic: Delay How to estimate delay and critical timing in CMOS circuits ? How to determine the proper transistor sizing in order to make a compromise with contradicting requirements ? How to choose the right circuit topology ? The Answer: “Logical Effort”


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