1. 10/20/05ELEC 5970-001/6970-001 Lecture 141 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Low-Power Logic Families Pass-Transistor Logic Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu

2. 10/20/05ELEC 5970-001/6970-001 Lecture 142 Low-Power Logic Styles Pass transistor logic Dynamic logic Domino logic Adiabatic and charge recovery logic Asynchronous logic Logic restructuring

3. 10/20/05ELEC 5970-001/6970-001 Lecture 143 Pass-Transistor Logic Requires fewer transistors –Smaller area –Reduced capacitance –Reduced energy and power

4. 10/20/05ELEC 5970-001/6970-001 Lecture 144 AND Gate A B F = AB 0 Need 4 transistors instead of 6 for CMOS gate.

5. 10/20/05ELEC 5970-001/6970-001 Lecture 145 Reduced Voltage Swing VDD = 2.5V IN OUT n transistors, W/L = 0.5μ/0.25μ p transistors, W/L = 1.5μ/0.25μ Vx = VDD – V tn

6. 10/20/05ELEC 5970-001/6970-001 Lecture 146 Spice Simulation Time, ns 00.5 1.0 1.5 2.0 3.0 2.0 1.0 0.0 Voltage, V IN OUT Vx J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003.

7. 10/20/05ELEC 5970-001/6970-001 Lecture 147 Voltage Transfer Characteristic (VTC) of AND Gate A B F = AB 0 n transistors, W/L = 0.5μ/0.25μ p transistors, W/L = 1.5μ/0.25μ

8. 10/20/05ELEC 5970-001/6970-001 Lecture 148 VTC: Spice Simulation Vin, V 00.5 1.0 1.5 2.0 2.5 3.0 2.0 1.0 0.0 F, V IN OUT B = VDD A = 0 → VDD A = VDD, B = 0 → VDD A = B = 0 → VDD VDD – V tn

9. 10/20/05ELEC 5970-001/6970-001 Lecture 149 Energy VDD = 2.5V 0 → VDD CL T E 0→1 =∫ P(t) dt= VDD ∫ i(t) dt0 VDD-V tn =∫ CL dVout= CL VDD (VDD – V tn ) 0 If this voltage is insufficient for turning the pMOS Transistor in inverter off, leakage power will be consumed. Vout i(t)

10. 10/20/05ELEC 5970-001/6970-001 Lecture 1410 Ways to Reduce Leakage Level restoration Multiple-threshold transistors Transmission-gate logic

11. 10/20/05ELEC 5970-001/6970-001 Lecture 1411 Level Restoration A B CL Vout VDDLevel restorer Level restorer device should be weaker than the nMOS pass transistor. Otherwise, VDD → 0 transition at Vout will be impossible. Switching threshold = VDD/2

12. 10/20/05ELEC 5970-001/6970-001 Lecture 1412 Multiple-Threshold Transistors Use zero-threshold pass-transistors. Use high-threshold transistors in all other gates. This can cause leakage through multiple gates.

13. 10/20/05ELEC 5970-001/6970-001 Lecture 1413 Leakage Through Zero-Threshold Transistors 0 1 1 0 Zero or low-threshold transistors Leakage current path

14. 10/20/05ELEC 5970-001/6970-001 Lecture 1414 Transmission-Gate Logic Provides both power and ground levels. Good design, except needs more transistors. ASBASB S’A’ + SB’ Inverting multiplexer

15. 10/20/05ELEC 5970-001/6970-001 Lecture 1415 Transmission-Gate XOR A AB’+A’B B

16. 10/20/05ELEC 5970-001/6970-001 Lecture 1416 Synthesis of PTL ABCZ 0000 0010 0100 0111 1000 1011 1101 1111 Shannon’s expansion: Z =AB + BC + AC =A(B+BC+C) + A’(BC) =A(B+C) + A’BC =A[B+B’C] + A’[BC] A 1 0 B CC10 Z

17. 10/20/05ELEC 5970-001/6970-001 Lecture 1417 Pass-Transistor Cell

18. 10/20/05ELEC 5970-001/6970-001 Lecture 1418 Synthesis of Z = A’B’ + BC’ + A’C B 0 A C Z

19. 10/20/05ELEC 5970-001/6970-001 Lecture 1419 Synthesis of Z = A’ + BC’ + B’C 0 B B’ A A’ C C’ Z

20. 10/20/05ELEC 5970-001/6970-001 Lecture 1420 Synthesis of Z = AB’C’ + A’B’C B B’ A’ A C’ C 1 Z

21. 10/20/05ELEC 5970-001/6970-001 Lecture 1421 CPL: Complementary Pass- Transistor Logic Every signal and its complement is generated. Gates are static, because the output is connected to either VDD or GND. Design is modular; same cell can produce various gates by simply permuting the input signals. Also called differential pass-transistor logic (DPL)

22. 10/20/05ELEC 5970-001/6970-001 Lecture 1422 A CPL Cell

23. 10/20/05ELEC 5970-001/6970-001 Lecture 1423 CPL Cell Used As AND/NAND A B A’ B’ B B’ Z = AB Z=(AB)’

24. 10/20/05ELEC 5970-001/6970-001 Lecture 1424 CPL Cell Used As OR/NOR A B A’ B’ B’ B Z = A+B Z=(A+B)’

25. 10/20/05ELEC 5970-001/6970-001 Lecture 1425 CPL Cell Used As XOR/XNOR A A’ A’ A B’ B Z = AB’+A’B Z= AB+A’B’

26. 10/20/05ELEC 5970-001/6970-001 Lecture 1426 References G. R. Cho and T. Chen, “On the Impact of Technology Scaling on Mixed PTL/Static Logic,” Proc. IEEE Int. Conf. Computer Design, 2002. R. Zimmermann and W. Fichtner, “Low- Power Logic Styles: CMOS Versus Pass- Transistor Logic,” IEEE J. Solid State Circuits, vol. 32, no. 7, pp. 1079-1090, July 1997.