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Latch versus Register Latch stores data when clock is low D Clk Q D Q Register stores data when clock rises Clk D D QQ.

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Presentation on theme: "Latch versus Register Latch stores data when clock is low D Clk Q D Q Register stores data when clock rises Clk D D QQ."— Presentation transcript:

1 Latch versus Register Latch stores data when clock is low D Clk Q D Q Register stores data when clock rises Clk D D QQ

2 Latches

3 Latch-Based Design N latch is transparent when = 0 P latch is transparent when = 1 N Latch Logic P Latch

4 Timing Definitions t CLK t D t c 2 q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ

5 Positive Feedback: Bi-Stability V o 1 V i 2 5 V o 1 V i 2 5 V o 1 V i1 A C B V o2 V i1 =V o2 V o1 V i2 V i2 =V o1

6 Meta-Stability Gain should be larger than 1 in the transition region

7 Writing into a Static Latch D CLK D Converting into a MUX Forcing the state (can implement as NMOS-only) Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

8 5.8 qCascade connection of pass transistors VVVV V Vo R C R C R C R C l = RC n(n+1)/2, n: number of stages(transistors) 1/2 n 2 RC l Vo can reach up to V-V TN V V V V Vo l Vo(high) = V-3V TN l Output of pass transistor better not be used as control variable for another gate.

9 qCases where pass tr. is appropriate l Multiplexer A B S S S

10 5.10 q4-input Multiplexer using CMOS switch concept Removing contacting & interconnecting wire segments saves space.

11 Y A conducting path must not exist between two different inputs which could take different logic levels. If there is an overlap between 1 and 2, the intermediate node y will take an undefined potential, located between the 1 and 0. This potential will give rise to an erratic behavior of the logic, although it may not be detected by a switch-level simulator This problem can be solved by designing control signal with a mutual exclusion feature qRules for transmission gate logic construction 1 X1 1 2

12 5.12 qRules for transmission gate logic construction 2 When a branch has several transmission-gates in series, internal nodes can behave as a dynamic memory Such a gate cannot be considered as a pure static combinational logic gate, because the memory effect can give rise to false outputs, according to the history of successive inputs and control levels, Moreover, the output could be at high impedance if no buffer has been provided. This behavior dramatically increases the simulation and test problems

13 5.13 qRules for transmission gate logic construction 3 1 a a aa 1 0 X1 X2 X1 X2 To avoid undesired high impedance states, care should be taken to always provide at least one conducting path between an input and the output The input variable sources must be low-impedance sources for the same reason Ex) 1-to-2 decoder wrong good

14 Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0D Q 0 1D Q

15 Mux-Based Latch

16 NMOS onlyNon-overlapping clocks

17 Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair

18 Master-Slave Register Multiplexer-based latch pair

19 Combinational logic circuit

20 Basic Latch Both circuit are the same The only feedback path is the red line

21 Basic Latch Consider Set = 0, Reset =0

22 Basic Latch Consider S = 1, R =0 As S=1, NOR1 output must be 0 As NOR1 ouput = 0 and R =0, NOR2 output must be 1

23 Basic Latch Consider S = 0, R =1 As R = 1, NOR2 output must be 0

24 Basic Latch Consider R = 1 and S =1 As R = 1, NOR2 output must be 0 As S = 1, NOR1 output must be 0

25 Level sensitive and edge sensitive For a latch and flip-flop (FF), it can be level sensitive or edge sensitive Level sensitive means the latch / FF will copy input D to output Q when Clk = 1 Edge sensitive means that the latch / FF will only copy input D to output Q when Clk change from 0 -> 1 (positive edge trigger) / 1 -> 0 (negative edge trigger)

26 Level sensitive

27 Edge sensitive


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