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Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory12 March 2002 CMS Tracker FED - Front End FPGA.

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Presentation on theme: "Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory12 March 2002 CMS Tracker FED - Front End FPGA."— Presentation transcript:

1 Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory12 March 2002 CMS Tracker FED - Front End FPGA DDR-DCI-I/O Frame_Sync_out Frame_Sync_In Readout_Sync_out Readout_Sync_In Monitor_Sync_out Monitor_Sync_In Data_stream Clock40 Reset ADC_Data_stream_0 ADC_Data_stream_11 Full Flags Front End FPGA delay_ser_out delay_ser_in Configuration JTAG Temp Sense Bank Voltages Core Voltage Bank DCI Resistors busy Clock XC2V1500FG I/O adc enables18 XC2V1000FG I/O Design I/O Total = 128 FE - BE I/O = 16 signals Config_in Config_out 3 Opto Rx6 2 x Temp Sense DAC Serial 4 8 Power downVBatt

2 Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory12 March 2002 CMS Tracker FED - Front End FPGA Floorplan ADC_Data FE-BE I/O Delay - Opto - ADC XC2V1500FG I/O XC2V1000FG I/O XC2V2000FG I/O XC2V3000FG I/O Same frame 456 & 676 ? Clocks? DiePackage Channel 0 Channel 11 Control

3 Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory12 March 2002 Front End Module Circuit 12 Channel Detector PD Array 3V 3.3V1.5V JTAG V DCM CLK40 XC2V XC2V40AD9218EL2140Opto Rx 6 FRS_OUT FRS_IN ROS_OUT ROS_IN CLOCK DC CNTRL DATA MO_OUT MO_IN DATA OUT 3 Full Partially Full RESET 100R 22R VD/3 8 ‘I2C’ >70° ~70° LM82 Thermal SL_OUT SL_IN +/-3.3V Signal Wired or


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