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1 IWORID 2002 David San Segundo Bello Design of an interface board for the control and data acquisition of the Medipix2 chip D. San Segundo Bello a,b,

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Presentation on theme: "1 IWORID 2002 David San Segundo Bello Design of an interface board for the control and data acquisition of the Medipix2 chip D. San Segundo Bello a,b,"— Presentation transcript:

1 1 IWORID 2002 David San Segundo Bello Design of an interface board for the control and data acquisition of the Medipix2 chip D. San Segundo Bello a,b, M. van Beuzekom a, P. Jansweijer a, H. Verkooijen a, J. Visschers a a NIKHEF, Kruislaan 409,1098 SJ Amsterdam, The Netherlands b MESA+Research Institute / University of Twente, Enschede, The Netherlands

2 2 IWORID 2002 David San Segundo Bello Outline Motivation and goals Board components Power supplies Data converters Control and data acquisition Conclusions Future work

3 3 IWORID 2002 David San Segundo Bello Motivation and goals Design and manufacture board for data acquisition and control of Medipix2 chip via conventional PC: MUROS2 Use off-the-shelf components. Fully digital control (PCI card used in PC handles only digital signals). Maximum flexibility: use programmable logic (Field Programmable Gate Array) Use serial communication implemented in Medipix2 chip. For 8 chips chipboard (see talk Alessandro Fornaini later today).

4 4 IWORID 2002 David San Segundo Bello CLOCK DAC bias DAC ext. DACs pulser ADC 2 x 8 SerDes FIFOs RX/TX LVDS RX/TX FPGA PC (DIO-653X) Medipix2 H.V. Supply / 32 / 16 / 16 /8/8 Muros2: block diagram Muros2

5 5 IWORID 2002 David San Segundo Bello Muros2: this is it

6 6 IWORID 2002 David San Segundo Bello Muros2 components: Overview Power supplies: -Medipix2 chips -Internal components Data converters: -4 DACs -1 ADC Voltage references (for data converters) Analog multiplexer (works with ADC) Clock source (7 MHz < f CK < 30 MHz) adjustable Digital transceivers (TTL to CMOS, etc…) FPGA (a.k.a. the brains)

7 7 IWORID 2002 David San Segundo Bello Must deliver power to the Medipix2 chips AND the internal components used in Muros2 : 2.2 V for Medipix2 chips: Analog (~ 300 mA /chip) Digital (~ 300 mA / chip) LVDS (~10 mA / chip) 1.8 V (~100 mA), 3.3 V (~100 mA) and 5 V (~300 mA) for the Muros2 components. Solution: Use 5V from National Instruments card Use external 3.3 V power supply: Linear regulators for 1.8 V and 2.2 V Muros2 components: Power Supplies

8 8 IWORID 2002 David San Segundo Bello Muros2 components: Data converters Digital to Analog Converters (DAC): -Bias DAC: control high voltage supply for detectors -External DAC: override one Medipix2 DAC -Pulser DACs: for analog test (more later…) Used National Semiconductors 14-bit DAC for all of them Analog to Digital Converter (ADC): Used for measuring values of DACs in Medipix2 chips. Analog multiplexer selects one out of 8 possible chips. Used Analog Devices 16 bit ADC

9 9 IWORID 2002 David San Segundo Bello Control & data acquisition: Overview Register controlled: registers in FPGA are used to control Muros2 (data converters, image acquisition modes….). 32 bit wide bus between NI card and Muros2:16 bits for asynchronous control signals (RESET, DATA/REG, etc…) and 16 bits for data transfer Data transfer between Muros2 and Medipix2: serial LVDS (data, clock and token) LVDS = Low Voltage Differential Signaling: Differential: good against E.M.I. and common-mode noise Low voltage: lower power dissipation, faster switching milliwatts) Data rates > 400 Mbit/s possible Why serial? Industry-wide and research move towards serial data communication schemes: serial ATA, PCI-Express, USB, FireWire, Gigabit Ethernet,…

10 10 IWORID 2002 David San Segundo Bello RESET Data / Registers Read / Write Acknowledge Request DATA CommunicationManager Stop Busy Ext. shutter Clock Reset Medipix2 Serial data DATA Control Shutter Enable (token) ANIN switch ADC DACs, etc... Clock Clock x 8 Control Medipix2 CommandsManager Registers FIFOs and SerDes Control & data acquisition: Blocks diagram

11 11 IWORID 2002 David San Segundo Bello Control & data acquisition: Registers I 12 registers inside the FPGA for controlling the Medipix2 as well as components in the Muros2 board: Configuration Register: Main control Counter: Control data transmission (count bits transmitted) Bias DAC: Control bias DAC Timer: Control shutter Frame counter : Control shutter External DAC: Control external DAC Pulse DAC values: Control DACs for analog test Pulse parameters: Parameters for analog test (number and duration of pulses) Read-only: Muros2 version number ADC control: Control ADC ADC value: Value from ADC (read-only) Extra I/O: Control extra 32- bit I/O connector for general-purpose use

12 12 IWORID 2002 David San Segundo Bello Control & data acquisition: Registers II Select for writing registers Select which register Prepare data in PC Begin data transmission Load high 16 bits Load low 16 bits

13 13 IWORID 2002 David San Segundo Bello Control & data acquisition: Data transmission FPGA implements: Data serialization: from 16-bit PC card (TTL levels) to 1- bit Medipix2 Data de-serialization: from 1-bit Medipix2 to 16-bit PC card LVDS transceivers (1-bit CMOS to/from 1-bit LVDS) not in our FPGA (size/cost), but LVDS is standard in most FPGA chips (Altera, Xilinx,…)

14 14 IWORID 2002 David San Segundo Bello Control & data acquisition: Shutter control Acquisition modes: Software controlled (with or without timer): Shutter opens by writing to one bit in one of the registers Hardware controlled (with or without timer): Shutter is controlled by an external signal Continuous acquisition (movie mode): Fully controlled by FPGA, so no latency due to software/computer

15 15 IWORID 2002 David San Segundo Bello Control & data acquisition: Analog test control Analog switch DAC 1 DAC 2 to input analog test Medipix2 chip FPGA Muros2 Medipix2 chipboard

16 16 IWORID 2002 David San Segundo Bello Conclusions Muros2 has been successfully used with Medisoft4 software to test 5 Medipix2 wafers Tests show that maximum data rates above 100 Mbit/s are possible. Main limitation seen so far is in maximum speed of Medipix2 chip: Muros2 alone can transmit/receive data at data rates > 160 Mbit/s Muros2 can evolve in the future thanks to having most functions implemented in FPGA (reprogramming)

17 17 IWORID 2002 David San Segundo Bello Future work Increase speed at chip level: new PhD project at NIKHEF/U. of Twente for high-speed (serial) data transmission Skip interface board (DIO-653X) between Muros2 and PC. (i.e. implementing PCI bridge in FPGA)

18 18 IWORID 2002 David San Segundo Bello NIKHEF: Ton Boerkamp, Alessandro Fornaini, Jan van Veen CERN: Xavier Llopart Czech T. U. (Prague): Tomas Horazdovski, Zdenek Kohout Univ. Napoli: Marino Maiorino (now in IFAE Barcelona), Cristina Montesi, Gianni Mettivier Univ. Erlangen: Michaela Mitschke Thanks to…


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