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First developments of DAQ\Trigger for RPC 30 October, 2002 General layout of OPERA DAQ\Trigger Naples activity Conclusions Adele Di Cicco Naples RPC Groups:

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Presentation on theme: "First developments of DAQ\Trigger for RPC 30 October, 2002 General layout of OPERA DAQ\Trigger Naples activity Conclusions Adele Di Cicco Naples RPC Groups:"— Presentation transcript:

1 First developments of DAQ\Trigger for RPC 30 October, 2002 General layout of OPERA DAQ\Trigger Naples activity Conclusions Adele Di Cicco Naples RPC Groups: Michelangelo Ambrosio, Lucia Consiglio, Adele Di Cicco, Giovanni Sorrentino In collaboration with the Naples SER group.

2 The single RPC plane readout FEB Padova Front End Boards ( 9 / plane ) Controller boards (22 / spectrometer) Trigger (or validation) board (1 / spectrometer) Vertical strip (2.6 cm) =334/plane Horizontal strip (3.5 cm)=228/plane Total strip 562/plane FEB developed in Padova 64 channels\board, divided into 2 groups of 32 channels

3 The Spectrometer DAQ scheme for the RPC Clock Trigger board Controller board Ethernet switch Clock signal from GPS central Unit RPC Planes: Signal from FE board (Fast OR) CLOCK Clock distribution card Validation trigger Plane ORs Ethernet Frascati, 30 Ottobre 2002

4 Controller Board (Specifications) Sets up thresholds, mask, polarity, etc… through serial link. Receives data and individual ORs from FEBs. Performs Plane OR and sends it to the trigger board. Performs data compression and data formatting (Zero suppression) Board housed in a VME crate (Links the time stamp to data) Frascati, 30 Ottobre 2002

5 Controller Layout FE Controller (Mask, Polarity, Threshold) FE Controller (Mask, Polarity, Threshold) FPGA Controller Ethernet Board Controller Ethernet Board clock FIFO Validate trigger Readout control FE readout FAST OR readout Plane OR to trigger Compressed Data FEB #0 FEB #1 FEB #9 FAST OR #0 FAST OR #1 FAST OR#18 Oscillator Frascati, 30 Ottobre 2002

6 Inside FIFOs Chain numberCluster AddressCluster size 5 bits 10 bits 3 bits Frascati, 30 Ottobre 2002 Word structure inside FIFO

7 Zero suppression ADD #0 ADD#31 Chain # ADD # ADD#31 5 bit for channel number (max 32) 10 bit cluster address (max 1024) 3 bit cluster dimension ( 7 consecutive strips fired ) Vertical strip (2.6 cm) =334/plane Horizontal strip (3.5 cm)=228/plane Total strip to address 562/plane ADD#31 Chain #1 Chain #5 Frascati, 30 Ottobre 2002

8 Trigger board (Specifications) Receives data from Controller boards (22 Plane OR) Performs majority between planes selected by the user Produces pattern of active planes Produces signal of validate trigger Receives GPS clock and sets time stamp for each event to be read out Frascati, 30 Ottobre 2002

9 About time stamp At the present the setting of time stamp for each event has been planned to be done on each controller board. This is due to the original layout in which the FEB acquisition is asynchronous (free running – no trigger). The use of a trigger signal allows the definition of the “trigger event time”: WE SUGGEST TO ASSIGN THE TIME STAMP TO THE TRIGGER TIME. 221 This solution allows the event building by reducing the needed information and the time stamp electronics from 22 to only 1 Frascati, 30 Ottobre 2002

10 DAQ readout operation Reads the time stamp from the trigger board Reads the trigger pattern from the trigger board Reads data from the controller boards of triggered planes only Frascati, 30 Ottobre 2002

11 Current activity in Naples Controller prototype Trigger prototype Local RPC test facility Local DAQ system In addition the group is involved in the RPC test in LNGS Frascati, 30 Ottobre 2002

12 Controller prototype Accepts up to 32 Fast ORs Performs the plane ORs for the trigger board Accepts the validation signal Reads up to 32 chains of max 1024 strips Performs the Zero suppression Writes data on FIFO 5 bit for channel number (max 32) 10 bit cluster address (max 1024) 3 bit cluster dimension Frascati, 30 Ottobre 2002 First of all we have modified an ARGO controller according to our requests Before Christmas we will complete tests on this first prototype An OPERA prototype will be produced within March 2003

13 Controller prototype board Controller Core VME interface FIFOs 4 of 20 input connectors (only 8 for channel and 8 for ORs are available). Frascati, 30 Ottobre 2002

14 Trigger prototype We are working on the following requirements: Prototype expected in March 2003: at the moment the trigger board is not necessary to test the controller board Majority of selected planes Possibility to impose fixed planes Pattern of fired plane Frascati, 30 Ottobre 2002

15 Existing RPC test facility in Naples Vertical telescope (16 planes) With two horizontal veto planes Horizontal telescope (6 planes) for electronic test bakelite RPC 1 x 2 m 2 Frascati, 30 Ottobre 2002

16 Local DAQ system in Naples Data acquisition by VME bus SBS 618 VME Use SBS 618 VME controller Collaboration with Nuclear Physicists ( EXOTIC group ) The EXOTIC group in Naples developed a data acquisition system based on VME bus very similar to the system proposed for OPERA. They agree to support us for installing a DAQ system for acquisition of test telescopes in Naples. Frascati, 30 Ottobre 2002

17 We are collaborating to the RPC test in LNGS RPC test in LNGS Frascati, 30 Ottobre 2002

18 Conclusions The Naples group is involved in the development of RPC readout electronics in collaboration with Lion and the rest of RPC group. The controller prototype is under electrical test. Results expected before Christmas. The trigger board is expected within March Frascati, 30 Ottobre 2002


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