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John Coughlan et al.Rutherford Appleton Laboratory14th May 20023rd CMS Electronics Week Tracker Front-End Driver Progress Report 3rd CMS Electronics Week.

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Presentation on theme: "John Coughlan et al.Rutherford Appleton Laboratory14th May 20023rd CMS Electronics Week Tracker Front-End Driver Progress Report 3rd CMS Electronics Week."— Presentation transcript:

1 John Coughlan et al.Rutherford Appleton Laboratory14th May 20023rd CMS Electronics Week Tracker Front-End Driver Progress Report 3rd CMS Electronics Week CERN May 14th 2002

2 John Coughlan et al.Rutherford Appleton Laboratory14th May 20023rd CMS Electronics Week CMS Tracker FED System Overview 96 ADC Channel 9U VME Board Layout DAQ CMC BE FPGA VME FPGA FED VME 64x 9U Transition Card TTS EXT CLOCK JTAG POWER FE “Modules” TTC S-LINK electrical AnalogueDigitalOptoRx 96 Fibre channels TTCrx Power Switchers QDR RAMs JTAG CONFIG BE “Module” FLASH EPROM Osc Digital Logic: FPGAs Target Family Xilinx Virtex II 40K -> 2 M gates CERN “Digitisation / Zero Suppression / Build for DAQ ”≈ 500 FEDs needed

3 John Coughlan et al.Rutherford Appleton Laboratory14th May 20023rd CMS Electronics Week Front End Module Circuit 12 Channel Detector PD Array 5V 3.3V1.5V 1 0V 12 way FR 1 1 Temp Sensing? JTAG? V V 10 5 LVDS DCM LVDS CLK40 XC2V XC2V40 AD9218 EL2140 CERN Opto Rx 6 FRS_OUT FRS_IN ROS_OUT ROS_IN CLOCK DC CNTRL DATA MO_OUT MO_IN DATA OUT 3 N Full Partially Full RESET 3.3V+/-5V Dual 10 bit FPGA ADCs OpAmps Clock Skew Sync & Cluster

4 John Coughlan et al.Rutherford Appleton Laboratory14th May 20023rd CMS Electronics Week CMS Tracker FED Front-End FPGA ADC 1 10 sync 11 trig2 Ped sub 11 trig3 Re-order cm sub 8 Hit finding s-data s-addr8 16 hit Packetiser 8 averages 8 header control DPM 16 No hits Sequencer-mux 88 a d a d ADC trig1 sync 11 trig2 Ped sub 11 trig3 Re-order cm sub 8 Hit finding s-data s-addr cycles hit DPM 16 No hits Sequencer-mux 88 a d a d status averages 8 headerstatus nx256x16 trig4 Synch in Synch out Synch emulator in mux Serial I/O Serial Int B’Scan Local IO Config Synch & Processing FPGA Full flags data Global reset Control Sub resets 10 Phase Registers Phase Registers 2 x 256 cycles256 cyclesnx256x16 trig1 Synch error 4x Opto Rx Delay Line Opto Rx Clock 40 MHz DLL 1x 2x 4x per adc channel phase compensation required to bring data into step + Raw Data mode, Scope mode, Test modes...

5 John Coughlan et al.Rutherford Appleton Laboratory14th May 20023rd CMS Electronics Week CMS Tracker FED Back End FPGA FIFO Circular Buffers Frame_Syncs Readout_Syncs Monitor_Syncs x8 TTC Rx TTS 9 ‘VME’ DECODE CONTROL & MONITOR Data_stream0 Data_stream Data In 20 Address 18 Data Out 64 SLINK 64 R/W Address Generator APV hdrs Lengths Bx,Ex Em Hdr diagnostics Data 80 Mhz 100 Khz MHz 40 Mhz Clock40 Reset DCM x1 x2 x4 QDR SSRAM x4 burst BSCAN 320 MHz 80 MHz Lengths Header FF/PF Flags Control

6 John Coughlan et al.Rutherford Appleton Laboratory14th May 20023rd CMS Electronics Week FED Hardware Status Front-End “Module” Circuit schematics done. Minor changes only. Provisional layout done. Detailed routing started. Components ordered for few off FF1s. Back-End “Module” FPGAs ordered. Most other components chosen and ordered. Power supply scheme done: +5.0, +3.3, +1.5, -5.0 V JTAG/Boundary Scan, chains provisional done. Clock distribution chain provisional done. Front-End “Module” Circuit schematics done. Minor changes only. Provisional layout done. Detailed routing started. Components ordered for few off FF1s. Back-End “Module” FPGAs ordered. Most other components chosen and ordered. Power supply scheme done: +5.0, +3.3, +1.5, -5.0 V JTAG/Boundary Scan, chains provisional done. Clock distribution chain provisional done.

7 John Coughlan et al.Rutherford Appleton Laboratory14th May 20023rd CMS Electronics Week FED “Software” Status FPGA Firmware: VHDL & Verilog Target Family Xilinx Virtex II Delay FPGA : Full logic is simulated/synthesized. Done. Front End FPGA : Full logic is simulated/ synthesized. Minor updates later. Back End FPGA : Basic fast data building to SLINK synthesized. DAQ header. More work needed to interface to TTC, local header, VME, monitoring. VME FPGA : Not done. Start with something simple. Software Design just starting. No register/memory map yet. Follow TriDAS models: Low level : Hardware Access Layer Higher level : Calibration, Monitoring … : XDAQ framework FPGA Firmware: VHDL & Verilog Target Family Xilinx Virtex II Delay FPGA : Full logic is simulated/synthesized. Done. Front End FPGA : Full logic is simulated/ synthesized. Minor updates later. Back End FPGA : Basic fast data building to SLINK synthesized. DAQ header. More work needed to interface to TTC, local header, VME, monitoring. VME FPGA : Not done. Start with something simple. Software Design just starting. No register/memory map yet. Follow TriDAS models: Low level : Hardware Access Layer Higher level : Calibration, Monitoring … : XDAQ framework

8 John Coughlan et al.Rutherford Appleton Laboratory14th May 20023rd CMS Electronics Week FED Test Test Sequence first boards Bare board PCB tests Assembled board : JTAG/Boundary Scan digital connectivity Pre-OptoRx : Analogue: Inject external signals + capture “Chip Scope” + JTAG readout Digital: FPGA configuration tests Test patterns in FPGAs Capture signals with programmed FPGAs VME readout Post-OptoRx: Opto Test Board DAQ S-LINK64 : TriDAS Hardware Resource Kit FED on board test facilities: Local clock, trigger, DAC VREF, FPGA Confign. Test Sequence first boards Bare board PCB tests Assembled board : JTAG/Boundary Scan digital connectivity Pre-OptoRx : Analogue: Inject external signals + capture “Chip Scope” + JTAG readout Digital: FPGA configuration tests Test patterns in FPGAs Capture signals with programmed FPGAs VME readout Post-OptoRx: Opto Test Board DAQ S-LINK64 : TriDAS Hardware Resource Kit FED on board test facilities: Local clock, trigger, DAC VREF, FPGA Confign.

9 John Coughlan et al.Rutherford Appleton Laboratory14th May 20023rd CMS Electronics Week Counting Room Layout 430 Boards96 ADC/Board 24 Crates 8 Racks 430 Boards96 ADC/Board 24 Crates 8 Racks 40 K ADC Channels10 Trigger Rate100 KHz Input Rate1.5 T Byte/s Output rate25 Gbyte/s/% 40 K ADC Channels10 Trigger Rate100 KHz Input Rate1.5 T Byte/s Output rate25 Gbyte/s/% 4 TTC Partitions? DAQ FED

10 John Coughlan et al.Rutherford Appleton Laboratory14th May 20023rd CMS Electronics Week FED FF1 Delivery Batch 0 (2 off) Assembled boards at RAL (except OptoRx) Sept 2002 Assemble OptoRx : Oct 2002 Batch 1 (N off) Manufacture (with OptoRx) May 2003 Delivery to CERN starting August 2003 Minimal requirement: Raw Data readout via VME. Any Questions? Batch 0 (2 off) Assembled boards at RAL (except OptoRx) Sept 2002 Assemble OptoRx : Oct 2002 Batch 1 (N off) Manufacture (with OptoRx) May 2003 Delivery to CERN starting August 2003 Minimal requirement: Raw Data readout via VME. Any Questions?


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