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Uli Schäfer Trigger Status JEP (JET/ENERGY PROCESSOR) Komponenten JEM0 (JET/ENERGY MODULE) -Hardware -Firmware JEM1 nächste Tests / Termine Production.

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Presentation on theme: "Uli Schäfer Trigger Status JEP (JET/ENERGY PROCESSOR) Komponenten JEM0 (JET/ENERGY MODULE) -Hardware -Firmware JEM1 nächste Tests / Termine Production."— Presentation transcript:

1 Uli Schäfer Trigger Status JEP (JET/ENERGY PROCESSOR) Komponenten JEM0 (JET/ENERGY MODULE) -Hardware -Firmware JEM1 nächste Tests / Termine Production Schedule

2 Uli Schäfer JEP 2 crates mit je: 16 JEMs (MZ, jet code : Stockholm)) 1 sum merger (CMM RAL / Firmware MZ) (VHDL V.0 code RAL (Andrea) 1 jet merger (CMM RAL / Stockholm ?) VMM (RAL) VME-MOUNT TCM (RAL) TIMING/CONTROL Backplane (Stockholm) CPU (cots) ROD crate mit RODs (RAL / MZ ?) READOUT DRIVER Alle Komponenten in Prototyp-Phase (slice test)

3 Uli Schäfer JEM0 Hardware (2 Module) :ok TTCrx (v.0) daughter / Stockholm (v.1?) (?) G-link line driver(?) Programmierbare Logikbausteine: 11 Input Processors(ok) Main Processor(jet / ROI?)(ok) Control FPGA(ok) ROC READOUT CONTROLLER (ok ?) CPLDs(ok) Wechsel der VHDL-Tools (HDL-Designer läuft nicht sauber mit Xilinx ISE5)

4 Uli Schäfer Functional blocks Real-time data path ok Control (VME, configuration)(ok) Monitoring (playback/spy) (ok) DAQ(??)

5 Uli Schäfer JEM1 Konzept PCB / assembly-Probleme bei JEM0 >>> Modulares Konzept 4 Input daughters - Input FPGA & de-serialiser ROC daughter – ROC & control (VME/config/CAN) (Neu: TTC, CAN, configuration f. Kompatibilität CPM) Main processor auf mainboard (1.28mm pitch) Neue FPGA-Typen (Virtex2) on-chip Serienterminatoren, 1.5V signalling

6 Uli Schäfer JEM1 Main Processor Input Processor 15* ' LVDS links 6 links per de-serialiser Config VME ROC TTC G G 15 x 6-channel de- serialisers : SCAN Input Processors : XC2V1500 Main Processor XC2V2000 DCS 6 VME

7 Uli Schäfer JEM1 Status Input daughter -PCB in Fertigung -Fertigungsprobleme -Lieferung in ca. 2 Wochen (KW24?) -Bestückung ca. 2 Wochen ROC -Design begonnen Mainboard ? Test boards -JTAG Testboard-Design begonnen -VME Testboard ? (Reinhold D. ?) -?? Adaptation JEM Firmware und Software

8 Uli Schäfer Sonstiges Latency assessment : JEM ok. Common merger ??? Tests und Termine Stockholm/Mainz Test in MZ 2.Juni > zu spät ????? RAL Test 16. Juni ROD review & QMW meeting: 30.6 / Weitere RAL Tests im Sommer


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