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The ESA MUSIC Project Design of DSP HW and Analog TX/RX ends Advanced Mobile Satellite Systems & Technologies presentation days ESA/ESTEC – 14-15 November.

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Presentation on theme: "The ESA MUSIC Project Design of DSP HW and Analog TX/RX ends Advanced Mobile Satellite Systems & Technologies presentation days ESA/ESTEC – 14-15 November."— Presentation transcript:

1 The ESA MUSIC Project Design of DSP HW and Analog TX/RX ends Advanced Mobile Satellite Systems & Technologies presentation days ESA/ESTEC – November 2000

2 AMSST Presentation Days – November 2000 Presentation Outline The PROTEO Signal Processing BoardThe PROTEO Signal Processing Board The MUSIC TX/RX Analog Signal Conditioning UnitsThe MUSIC TX/RX Analog Signal Conditioning Units

3 AMSST Presentation Days – November 2000 The PROTEO Signal Processing Board

4 AMSST Presentation Days – November 2000 The PROTEO Signal Processing Board

5 AMSST Presentation Days – November 2000 PROTEO Functional Block Diagram

6 AMSST Presentation Days – November 2000 PROTEO Board Main Features Summary 12 bit pipelined ADC Converter (BB ADS807) up to 53MHz sampling. 100 Kgates CPLD (Altera Flex EPF10K100A): - clock >100MHz; - usable gates: 90%; - embedded array blocks: 12 (ex. RAM, ROM, FIFO functions); - in-circuit re-configurability via Byte-Blaster or JTAG port. 66 MIPS 16bit DSP (ST18952). On board Memories: - x CPLD: SRAM 256Kx16 & SIMM-like Module for SRAM 1MB or SDRAM 4MB; - x DSP : SRAM 64Kx16, FLASH 4Mx16. Master Clock distribution by Prog. Skew Clock Buffer (Cypress CY7B991): - selectable skew to 18ns (+-12 time units of 1.5ns). Prog. Clock Generator (Cypress ICD2053B) for CPLD only: - clock out : 391KHz-90MHz; - prog. "on the fly" by 2 wire serial interface. 2x 12 bit dual DAC converters (Analog Device AD5323) : - high-speed serial interface control logic (up to 30 MHz).

7 AMSST Presentation Days – November 2000 PROTEO Clocks Distribution

8 AMSST Presentation Days – November 2000 MUSIC Breadboard System Overview

9 AMSST Presentation Days – November 2000 MUSIC TX - System requirements IF Carrier Frequency: 70MHz Max Carrier Frequency Uncertainty: +/-100 Hz TX Output Power Level: -10 to -30 dBm Spurious and Harmonics: <40 dBc In-Band Ripple: <0.1 dB

10 AMSST Presentation Days – November 2000 The MUSIC TX/RX: Analog IF Front End

11 AMSST Presentation Days – November 2000 Up-conversion TX board Block Diagram LC Butterworth Low-pass Filter Order: 5 3-dB Bandwidth: 7.5 MHz Active Mixer: Analog Device AD831 LO Drive required (min): -10 dBm P1dB: +10 dBm IP3: +24 dBm SAW Filter: SAWTEK dB Bandwidth: 3.25 MHz Insertion Loss: 7.7 dB In-band ripple: dB Group delay in spec TCXO: Fordahl DFA 36-MS Nom Frequency: MHz Output Load: Sine 0 dBm (50 Ohm) Frequency stability: +/- 1 ppm

12 AMSST Presentation Days – November 2000 P1dB Measurements P1dB (input): +10 dBm

13 AMSST Presentation Days – November 2000 Harmonics and in-band ripple Max Outband spurious level: -44 dBc In-band ripple (Pin=0dBm) : 1 dB Isolation LO to Output: -65 dB

14 AMSST Presentation Days – November 2000 MUSIC RX AGC board Block Diagram error signal VGA: Philips SA5219 Bandwidth: 700 MHz 7 dB Noise Figure Min 0-1V gain control pin SAW Filter: SAWTEK dB Bandwidth: 3.25 MHz Insertion Loss: 7.7 dB In-band ripple: dB Group delay in spec RSSI: Analog Devices AD8307 Dynamic range: 92 dB Slope: 25 mV/dB Op-Amp: TSH31 Op-Amp: TL082 1 pole RC filter

15 AMSST Presentation Days – November 2000 Control loop IF 70MHz 1V p-p Diff.out Signal +MAI +Noise to MUSIC Receiver Digital Section fIF IF N BALUN B-P Filter 2 RX SECTION TP VGA 1VGA 2 TP Vref - + Amp2 Amp1 BUFFER LOG AMP RSSI Low-Pass filter Loop stability!! Loop error Loop gain Loop Bandwidth

16 AMSST Presentation Days – November 2000 Loop Bandwidth Loop Bandwidth must be limited in order to avoid input signal modulation. Loop bandwidth fixed: 200 Hz Loop gain: ~20 dB

17 AMSST Presentation Days – November 2000 HP-ADS Simulation Schematic

18 AMSST Presentation Days – November 2000 HP-ADS Simulation Input Signal Input Signal Average Power Dynamics: 20 dB Average Fading rate: 20dB/3ms

19 AMSST Presentation Days – November 2000 HP-ADS Simulation Results 20 dB Input Power Dynamics 1 dB Output Power Dynamics

20 AMSST Presentation Days – November 2000 Conclusions Implementation of TX and RX boardsImplementation of TX and RX boards Testing and measurements has confirmed simulations resultsTesting and measurements has confirmed simulations results


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