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ISIS and SPiDeR Zhige ZHANG STFC Rutherford Appleton Laboratory.

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Presentation on theme: "ISIS and SPiDeR Zhige ZHANG STFC Rutherford Appleton Laboratory."— Presentation transcript:

1 ISIS and SPiDeR Zhige ZHANG STFC Rutherford Appleton Laboratory

2 Content ISIS Concept –ISIS1 ISIS2 –Design –test structure –ISIS2 So far SPiDeR –Project –Sensors Z Zhang Vertex 2009 Putten 2

3 ISIS Concept In-situ Storage Image Sensor Parallel sampling for all the pixels Store the raw charge locally ( next to the pixels) Read out later Fast frame rate but limited number of frames Burst events such as ILC bunch train Z Zhang Vertex 2009 Putten 3

4 Image sensor ISIS has been used in image sensor for high speed camera –Frames rate: 10 6 Frames/Second –Sensor size: 312x260 –Frames storage: 103 frames ETOH et al. IEEETRANS ELECTRON DEVICES, 50, (2003) pp Z Zhang Vertex 2009 Putten 4

5 ISIS1 Test of concept –16 X 16 image pixels –5 storage cells –CCD process –Pixel size 160 X 40 µm Z Zhang Vertex 2009 Putten 5 p+ shielding implant n+ buried channel (n) Charge collection reflected charge High resistivity epitaxial layer (p) Sense node (n+) row select reset gate V DD Photogate transfer gate Output gate to column load Storage cell #1 - 5 substrate (p++) Isolation gate

6 ISIS1 Z Zhang Vertex 2009 Putten 6 Zhang et al Nucl. Instr. and Meth. A 607 (2009) pp Deep p-well charge shielding on storage pixels Ratio of x-ray events on photo gate and storage cells –(a) without –(b) with (GV = 4V) –(c) with (GV = 8V) Deep p-well works

7 ISIS2 Second generation of ISIS Miniature design 20X20 µm 2 pixel size: 0.18 µm CMOS process non–overlapping gates Deep p-well for charge shielding Z Zhang Vertex 2009 Putten 7

8 ISIS2 Cross Section Z Zhang Vertex 2009 Putten 8 p+ shielding implant Charge injector buried channel (n) Charge collection p+ well reflected charge High resistivity epitaxial layer (p) Storage pixel #1-20 Sense node (n+) Row select Reset gate Source follower V DD Photo gate Reset transistor Row select transistor Output gate Output substrate (p+) Summing gate

9 ISIS2 Test structure –Small version of one pixel –Photo, Summing and Output gate –Readout electronics Allows test of basic functionality –Charge transfer –Readout –Fringe effect Z Zhang Vertex 2009 Putten 9 IDR IG PG SG OG RG RD OD RSEL M0 OS SS ISIS2 test structure

10 ISIS2 Low noise on readout electronics –Measure the x-ray events on the output node –5.5 e - (STD) with CDS (800ns) –Clear 55 Fe K peak –1620/145 = e - /ADC –24 µV/e - Z Zhang Vertex 2009 Putten Fe K

11 ISIS2 High resistance on the gate Examined by connecting test structure as a big transistor 100 Hz applied to gate yellow line Green line is the output However the test structure can be controlled by slow clocking Z Zhang Vertex 2009 Putten 11

12 Charge capacity Z Zhang Vertex 2009 Putten 12 Pixel size 1X5 µm Gate voltage = 3.5V Charge capacity inside linear part –~ C –~ C –~ C –Close to the design

13 ISIS2 Dark Current Dark current collected under the 1x5 µm 2 Temperature range -10 to 20 C Unit: e- / ms Isolated pixel only A guidance for the testing Z Zhang Vertex 2009 Putten 13

14 ISIS2 Fringe Effect Potential under the output gate is pulled up by output node(5V) Charge leaked to output node directly from photo gate -0.2 V is the best setting for this device Several ways to modify the design Z Zhang Vertex 2009 Putten 14

15 ISIS2 main array Z Zhang Vertex 2009 Putten 15 One pixel Whole sensor 20 storage cells buried channel CCD Pixel size 80x10/20x40 µm 2 Storage cell charge capacity > 6ke - 256x32 pixels

16 ISIS2 55 Fe events on main array Beginning of the study on main array Challenges –Slow clocking –Dark current –Charge transfer Z Zhang Vertex 2009 Putten 16 Y Li Oxford

17 SPiDeR Silicon Pixel Detector R&D Continue and extend the sensor development in previous projects (CALICE and LCFI) –Goal: further develop monolithic silicon active pixel detectors Vertexing, tracking and electromagnetic calorimetry The sensors include –TPAC (CALICE) –CHERWELL ISIS (LCFI) (Charge Coupled CMOS) FORTIS –a demonstrator device for 4T (pinned photodiode) technology Digital Calorimeter test stack Z Zhang Vertex 2009 Putten 17

18 TPAC Z Zhang Vertex 2009 Putten 18 Tera-Pixel Active Calorimeter, it has per-pixel peramp, thresholding and timestamp capability

19 TPAC stack behind testbeam CERN Aug 19 Z Zhang Vertex 2009 Putten

20 FORTIS in testbeam testbeam CERN Aug, Fortis sanwiched between elements of the EUDET Si telescope Z Zhang Vertex 2009 Putten 20

21 Hits on FORTIS testbeam CERN Aug 21 Z Zhang Vertex 2009 Putten

22 22 Thanks


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