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1 Introduction to CMOS Technology C. Fenouillet-Beranger SOI Devices Engineer, CEA/LETI & STMicroelectronics, Crolles.

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Presentation on theme: "1 Introduction to CMOS Technology C. Fenouillet-Beranger SOI Devices Engineer, CEA/LETI & STMicroelectronics, Crolles."— Presentation transcript:

1 1 Introduction to CMOS Technology C. Fenouillet-Beranger SOI Devices Engineer, CEA/LETI & STMicroelectronics, Crolles

2 2 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Outline p MOSFET Basics –Ideal MOSFET physics –Main parameters : threshold, leakage and speed –What MOSFET for what application ? –Scaling theory and good design rules of CMOS Devices p The Real World –Threshold voltage control limitations –Gate oxide leakage and capacitance scaling p Technological Solution ? –Gate alternative : High-K and Metal Gate –Channel engineering : Strained-Si –Alternative devices and substrates –Basic logic functions

3 3 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 MOSFET Basics

4 4 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 CMOS technology applications

5 5 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Different scales inside a chip 2x2 cm² 10x10 mm² 4x4 µm² 500x500 nm² Silicon channel NiSi Source Drain Gate

6 6 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Making a Switch with Metal, Oxide and Silicon Energy Barrier x Carrier reservoir Source Drain E Energy Barrier x Carrier reservoir Source Drain Metal Oxide Si (p) n+n+n+n+ n+n+n+n+ 0 Vg = SD C Vd

7 7 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 What is an ideal MOS Transistor ? V S =0VV D >0V V G =0V S D G + + + - - - - - - - V S =0VV D >0V V G >0V S D G I DS Canal vide : courant nulCanal rempli : courant non nul AB TMOS bloquéTMOS passant OFF-STATE ON-STATE A MOS capacitor is modulating the transport between two carrier reservoir MOSFET MOS capacitance : Field Effect MOSFET

8 8 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 n-type & p-type MOSFETs nMOSFET Electron conduction pMOSFET Hole conduction Metal Oxide 0 Vg<0 p+p+p+p+ p+p+p+p+ Si (n) Vd<0 Metal Oxide Si (p) n+n+n+n+ n+n+n+n+ 0 Vg>0 Vd>0

9 9 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Si MOSFET morphology Gate (Poly-Si) SourceDrain Métal Oxyde Semi- conducteur

10 10 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Basic Physics of MOSFET V gate Log(I drain ) Ideal switch Threshold (V th ) ON state Current OFF state Current MOSFET switch OFF State Current (Thermal) 3 main parameters 1.Threshold Voltage 2.Ion (=speed) 3.Ioff (=stand-by power)

11 11 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 MOSFET Physics L W S/C W D/C sourcedrain grille canal BC N P d - - - - - - N - - - - - - V G =0 VDVD VSVS VBVB L Tox « Off State» N P N + + ++ - - - - - - nMOSFETL W S/C W D/C sourcedrain gate channel BC P N VDVD N - - - - - - - - - - - - V G =V D VDVD VSVS VBVB L Tox N P N - - - - - - - - + + + + +

12 12 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Threshold Voltage (V th ) L W S/C W D/C sourcedrain gate channel BC P N VDVD N - - - - - - - - - - - - Gate Material Oxide Thickness Channel Doping

13 13 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 On State Current (I on ) L gate Source Drain Gate L Vg-Vth Vg-Vth-V DS

14 14 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Off – State Current (I off ) --- --- V D >0 V G1 0 V G1 { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/1682718/6/slides/slide_13.jpg", "name": "14 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Off – State Current (I off ) --- --- V D >0 V G1 0 V G1 0 V G1 0 V G1

15 15 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 The Static Leakage Components i) Gate leakage (oxide thickness dependance) iii) Junction leakage (doping dependance) ii) Channel Leakage (Vth and S dependant) I off = IS + IG + IB

16 16 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Different Applications : Some typical numbers Operation Speed Power Dissipation Computers Mobile Phones Hifi – TV Low Vth High Vth

17 17 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 CMOS Scaling CMOS090 CMOS065 CMOS045 CMOS032 CMOS120

18 18 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Gordon Moore, a co-founder of Intel said in 1965: Component count per unit area doubles every two years -Last 40 years : technological advances achieved mainly by reducing transistors size - However current trend of miniaturization causes undesired effects degrading the electrical parameters and transistor performance Scaling Theory: Moores law In reality: µ decreases Tox levels-off Off current increases as transistor size is reduced

19 19 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Ideal MOSFET Basics summary On-State : On-State : MOS gate capacitance lowers channel barrier electrons(holes) flow from Source to Drain I on current Carrier transit time is Cgate*Vgate / I on the higher Ion the faster the device Off-State : Off-State : MOS gate capacitance potential = 0 electrons(holes) flow from Source to Drain due to Thermionic current I off current Static Power dissipation is P stat = V DS * I off Threshold Voltage : Threshold Voltage : Determines the gate voltage transition V th between Off-state and On-state regimes Vth depends (at the 1st order) on the channel doping and gate electrode material

20 20 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Part 2. The Real World

21 21 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 V th Control : Short Channel Effects Zone de charge despace ZCE L BC SCE=Short Channel Effect SCE DIBL DIBL=Drain Induced Barrier Lowering V DS V th Log I drain V gate SCE Vth 1 DIBL Vth 2

22 22 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 MOSFET Typical Lenghts and Ratios L gate,phys drain gate T dep source L el XjXj T ox ; ; 3 1 el j 30 40 1 el ox L T 3 1 el dep L T L X 5 1 dd th V V Good design rules of MOSFET architecture :

23 23 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 ds el dep el ox el j ox Si V L T L T L X DIBL 2 2 1 bi el dep el ox el j ox Si V L T L T L X SCE 2 2 1 0.8 dsatgoxeffdsat V(V(V L el W el CI 2 1 -V th ) T. Skotnicki et al. IEEE EDL, March88 & IEDM1994 Scaling rules (MASTAR Model) V TH (short Mosfet)=V TH (long)-SCE-DIBL

24 24 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Why is it so difficult to get a « Good Scaling » ? L gate,phys drain gate T dep source L el XjXj Oxide ScalingJunction Scaling Subthreshold control Doping increase

25 25 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 T ox /L el ratio : Gate Oxide Scaling L gate,phys drain Poly-Si gate T dep source L el XjXj zz

26 26 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 The Gate-Poly Silicon Depletion Ref.: E. Josse et al., IEDM99 N+ P+ T dep poly = 0.4nm 0.6nm Vddscaled withTox

27 27 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Quantization Effects in Inversion Layer C-Y. Hu et al., IEEE EDL, June 1996 ~150mV

28 28 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Impact on Good Design Rule Tox,eff = Tox + 8A Good design Rule Reality

29 29 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 The problem of Gate Leakage Poly-Si Si Ef Ev Ef Ec Gate N+ SiO 2 Substrate Si P Ec Ev W pd 2A reduction in T ox ~ 1 dec increase in gate leakage 2

30 30 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Impact of Gate Leakage on Circuits In Static Mode, two gate leakages: Ig Off & Ig On : increase of Ioff If Tox, Ig, Power 0 1 0 0 Ioff canal Ig off 1 0 0 0 Ig On

31 31 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 V th /V dd Ratio If V dd drops, just decrease the V th too keep a good Ion. But … S degrades at smaller L ! V gs V th Log(I DS ) I off

32 32 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 What Did We Learn ? Controlling V th ( I off ) Increasing Doping Scaling Jonctions Scaling Tox DarkspacePolydepletion Junc. Leak. Rs increase I on (speed) reduction I off (power) increase Higher I off Limited Scaling I on reduction Gate leakage Reducing Vdd (power) Reducing Vdd (power) I on reduction

33 33 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Technological Boosters to recover a Healthy Scaling

34 34 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 What can we do to retrieve a Healthy Scaling ? Silicon channel NiSi Source Drain Gate Oxide ScalingJunction Scaling Subthreshold control Vs Overdrive Doping increase Less Gate Lekage No Poly Depletion DIBL-Free Architecture Low RSD for lower Xj Better Contact Resistance Better Ion at the same overdrive Better Subthreshold Slope

35 35 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Mobility Enhancement

36 36 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 I on Enhancement by materials Transistor Architecture Material Properties Carrier velocity under electric field E in the linear regime: v = µ E µ E critical E field Velocity Velocity saturation regime

37 37 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Mobility In Silicon E carrier, mass m* Shockwave from lattice vibration, or impurities, or gate oxide rugosity every seconds 1.Small m* : ligth electrons or holes * 2 m E v c 2. High (less possible collision) * m qµ Effective mass of carrier Linked to valence/conduction bands

38 38 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Who are the guys responsible for I on ? Silicon Band Structure mlml mtmt (x)100 (y) 010 (z) 001 6 equivalent types of electrons are involved in conduction regime of nMOS 2 types of holes are involved in conduction regime of pMOS : heavy and light

39 39 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 What happens in Strained-Si ? Splitting Sub-band Carrier Redistribution Band structure deformation Splitting less intervalley phonon scattering

40 40 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Redistribution in subbands and scattering reduction Strained-Si < 1 % in HH Unstrained Si >80 % in HH E N Fermi-Dirac

41 41 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Is Stress the Only Way to Enhance Mobility ? p Carrier effective mass can depend on cristal direction ! –For Electron iso-energy are ellipsoidal average dependance does not depend on Si direction for standard (100) substrate (not true in other direction) –For Hole : extremely high anisotopy of mass !! Heavy Mass Light Mass Holes with the same energy Cristal Direction (3D)

42 42 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Choosing the right Si-orientation for Holes Heavy Mass along transport Standard channel Standard (100) wafer Light Mass along transport Rotated channel 45° Rotation

43 43 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Optimum Cristal Orientations From M.Yang et al., IEDM 2004 nMOS pMOS Inversion layer mobility depends on the surface orientations and current flow directions For holes, mobility is 2.5x higher on (110) surface compared to standard wafer with (100) orientation For electrons, mobility is highest on (100) substrates

44 44 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Hybrid integration [M. Yang et al., IEDM 2003] To fully take advantage of the carrier mobility dependence on surface orientation, fabrication of CMOS on hybrid substrates has been demonstrated The hybrid substrate is obtained using a layer transfer technique in which the bonded wafer and the handle wafer have different crystal orientation. An additional photo step is used to etch through the SOI and BOX and expose the surface of the handle wafer to perform SEG Issues : limited scalability of bulk devices and increased process complexity

45 45 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Mobility Enhancement Techniques Substrate-based BULKSSOI Si x Ge 1-x Based BulkSSOI Tensile bi-axial stress nMOS+pMOS Si SiGe box SiGe SD Compressive pMOS SiGe SEG Process-based Induced Stess Liners CESLSMT nMOS Tensile nMOS Tensile pMOS Compressive Cristal Orientation In-plane Out of plane Mod.Orientation Si Channel pMOS Natural mobility boost Rotated substrate Cristal Orientation STI SACVD Tensile Bi-axial nMOS+pMOS

46 46 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Strain and mobility Low field mobility ElectronsHoles Biaxial tensile ++ Biaxial compressive -+ Uniaxial tensile (along L g ) +- Uniaxial compressive (along L g ) -+ Uniaxial compressive (along L g ) Biaxial tensile Uniaxial tensile (along L g ) [F. Payet, L2MP PhD, 2006]

47 47 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Uniaxial Stress By Stressed-Liner 2D mecanical Simulations Impact on nMOSFETs performances Tension Strained MOSFET (Lg=30nm) by CESL CESL Tensile (F.Bœuf et al., IEDM 2004, SSDM 2004)

48 48 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Hole Mobility enhancement using Rotated Substrates 45° Current Flow

49 49 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Uniaxial Stress using SiGe S/D T.Korman Courtesy, F.Payet unstrained +15%

50 50 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Gate Capacitance Scaling : High-K dielectrics

51 51 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Figthing against Gate Leakage Ef Ev Ef Ec Gate N+ SiO 2 Substrate Si P Ec Ev W pd Reducing Tunneling… Increasing T ox ! But without reduction of Cox ! Increasing permitivity HIGH K materials Leakage issue Polydepletion issue Replacing Poly-Si by Metal

52 52 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 52 Context Down to 90nm gate length, N+ and P+ polysilicon gate was used for CMOS integration compatible with oxide or oxynitride gate dielectric. Due to aggressive scaling of the gate dielectric, the gate leakage is becoming unacceptably high (>Ioff), requiring the use of high-k dielectric Due to the incompatibility of polysilicon gate with high-k dielectric (Fermi pinning, large Vt, mobility degradation) and the need to boost performance (elimination of polydepletion, boron penetration,…), metal gate electrodes will likely be needed For bulk technology, two metals with WFs close to the bandgap edges are needed (high channel doping required to control SCE). For FDSOI or double gate devices, WFs within 250meV from midgap are preferred, requiring more complex integration Two integration approaches are considered: gate first and gate last. Figthing against Gate Leakage

53 53 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 53 High-k dielectric C. Fenouillet et al IEDM 2007 High-K At an equivalent CET of SiON dielectric, the gate leakage current is reduced by more than 2 decades p For EOTs below 20Å, gate leakage current becomes higher than off-state leakage current. High-k dielectric p High-k (HfO2, ZrO2, Hf-based or Zr-based, LaO2, Al2O3,… ALCVD or MOCVD deposition p Pre-deposition clean and post deposition anneals affect the quality of high-k p Large Vt: Fermi pinning at the poly-Si/ Metal oxide interface but occurs also metal gate electrodes Compatibility of polysilicon gate with high-k is unlikely !

54 54 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 54 High-k Dielectric : Issues p Mobility degradation - Many publications have reported mobility degradation using high-k dielectrics. -Possible cause is coupling of soft optical phonons in high-k with inversion channel charge carrier p Vt instabilities and reliability and noise issues p Large k and large dielectric thickness result in fringing field (FIBL) and loss of control of the channel by the gate B. Tavel et al, PhD Thesis 2002

55 55 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Gate Capacitance Scaling : Metal Gates

56 56 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Choosing The « Good Metal » Mid-gap Gate Ec Ev nMOS Gate poly-Si N+ Metal Gate « N+like » 1.12V pMOS Gate poly-Si P+ Metal Gate « P+like »

57 57 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 57 p The use of metal gate suppress: –the polysilicon depletion : a reduced CET of 3-5Å for performance improvement –and suppress the boron penetration problem p Two approaches have been proposed: gate first or gate last –Gate first approach requires to take care of FE contamination tool, metal etching and to the high temperature anneal –Gate last approach (replacement gate): dummy gate removal and replacement, gate dielectric integrity has to be kept But for some applications CMOS requires 2 different metal gates in order to separate WFs for NMOS and PMOS devices (Dual metal gate integration) Metal gate integration

58 58 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Why is Metal Workfunction so important ? VgVg Log I d IdId VgVg V th,n V th,p I on,n I on,p V dd Regular Poly-gate n+/p+ VgVg IdId VgVg V th,n V th,p I on,n I on,p V dd Mid-gap Metal Gate +0.5V VgVg Log I d IdId VgVg V th,n V th,p I on,n I on,p V dd Dual n+/p+ Metal Gate Log I d +25% Polydep reduction

59 59 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 59 Why midgap metal gate ? Why high-k ? Midgap electrode with undoped channel : symmetrical V th for NMOS and PMOS for high Vth applications With Band edge gate electrodes (as poly-Si), FDSOI requires very high channel doping > 8e18 at/cm3 for HVT -> Variability degradation Metal gate interest for FDSOI

60 60 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Device Architecture

61 61 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Bulk PD SOI Scalability ? Scalability as BULK Scalability much improved if GP FD SOI Scalability may be better or worse (GP,BOX) FD SON GP Scalability very much improved DG (Delta, FinFET, SON, Vertical, TriGate, Omega, etc., etc. Xj T dep REF.:T. Skotnicki, invited paper ESSDERC 2000, pp. 19-33, edit. Frontier Group Device Architecture

62 62 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Layout and basic functions

63 63 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Logic Applications Complex Function (MP4 Decoder, µProc, Motion Detector, TVDH …) Layout inverter NAND SRAM Basic Functions Layout Silicon

64 64 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Layout of the transistor isolation Si=Active GateSourceDrain Gate SourceDrain Metal 1 Contact Contact Contact Metal Oxide Si (p) n+n+n+n+ n+n+n+n+ 0 Vg>0 Vd>0

65 65 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Design rules p Design Rule Manual (DRM) –Document that gives the design rules for a technology node –Gives the minium dimensions for each level –Give the minium distance between two levels p The design rules give the maximum density achievable for a technology node Si=Active L poly W Diam. contact Poly-active Poly-contact Active- contact

66 66 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 Circuit cross-section InterconnectTransistors

67 67 C.Fenouillet-Beranger; Techno des CI – PHELMA 2A 2011 FEOL & BEOL Metal 1 Metal 2 Metal 3 Metal 4 Metal 5 Metal 6 MOSFETs FEOL=Front End of Line BEOL = Back End Of Line


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