1. Optional Reading: Pierret 4; Hu 3
Lecture 23
OUTLINE
The MOSFET (cont’d)
Source/drain structure
CMOS fabrication process
The CMOS power crisis
Reading: Pierret 19.2; Hu 6.10
Optional Reading: Pierret 4; Hu 3

2. Source and Drain (S/D) Structure
To minimize the short channel effect and DIBL, we want shallow (small rj) S/D regions  but the parasitic resistance of these regions increases when rj is reduced.
where r = resistivity of the S/D regions
Shallow S/D “extensions” may be used to effectively reduce rj with a relatively small increase in parasitic resistance
EE130/230A Fall 2013
Lecture 23, Slide 2

3. E-Field Distribution Along the Channel
The lateral electric field peaks at the drain end of the channel.
Epeak can be as high as 106 V/cm
High E-field causes problems:
Damage to oxide interface & bulk
(trapped oxide charge  VT shift)
substrate current due to impact ionization:
EE130/230A Fall 2013
Lecture 23, Slide 3

4. Lightly Doped Drain (LDD) Structure
Lower pn junction doping results in lower peak E-field
“Hot-carrier” effects are reduced
Parasitic resistance is increased
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 19.9
EE130/230A Fall 2013
Lecture 23, Slide 4

5. Parasitic Source-Drain ResistanceG RS RD S D
For short-channel MOSFET, IDsat0  VGS – VT , so that
 IDsat is reduced by ~15% in a 0.1 mm MOSFET.
VDsat is increased to VDsat0 + IDsat (RS + RD)
EE130/230A Fall 2013
Lecture 23, Slide 5
C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 7-10

6. Summary: MOSFET OFF State vs. ON State
OFF state (VGS < VT):
IDS is limited by the rate at which carriers diffuse across the source pn junction
Minimum subthreshold swing S, and DIBL are issues
ON state (VGS > VT):
IDS is limited by the rate at which carriers drift across the channel
Punchthrough is of concern at high drain bias
IDsat increases rapidly with VDS
Parasitic resistances reduce drive current
source resistance RS reduces effective VGS
source & drain resistances RS & RD reduce effective VDS
EE130/230A Fall 2013
Lecture 23, Slide 6

7. CMOS Technology
Need p-type regions (for NMOS) and n-type regions (for PMOS)
on the wafer surface, e.g.:
(NA)
(ND)
n-well
Single-well technology
n-well must be deep enough
to avoid vertical punch-through
p-substrate
(NA)
p-well
(ND)
n-well
Twin-well technology
Wells must be deep enough to avoid vertical punch-through
p- or n-substrate
(lightly doped)
EE130/230A Fall 2013
Lecture 23, Slide 7

8. Sub-Micron CMOS Fabrication Process
A series of lithography, etch, and fill steps are used to create silicon mesas isolated by silicon-dioxide
Lithography and implant steps are used to form the NMOS and PMOS wells and the channel/body doping profiles
EE130/230A Fall 2013
Lecture 23, Slide 8

9. The thin gate dielectric layer is formed
Poly-Si is deposited and patterned to form gate electrodes
Lithography and implantation are used to form NLDD and PLDD regions
EE130/230A Fall 2013
Lecture 23, Slide 9

10. A series of steps is used to form the deep source / drain regions as well as body contacts
A series of steps is used to encapsulate the devices and form metal interconnections between them.
EE130/230A Fall 2013
Lecture 23, Slide 10

11. CMOS Technology Advancement
XTEM images with the same scale
courtesy V. Moroz (Synopsys, Inc.)
90 nm node
65 nm node
45 nm node
32 nm node
T. Ghani et al.,
IEDM 2003
(after S. Tyagi et al., IEDM 2005)
K. Mistry et al.,
IEDM 2007
P. Packan et al.,
IEDM 2009
Gate length has not scaled proportionately with device pitch (0.7x per generation) in recent generations.
Transistor performance has been boosted by other means.
EE130/230A Fall 2013
Lecture 23, Slide 11

12. Performance Boosters Strained channel regions  meff
High-k gate dielectric and metal gate electrodes  Coxe
Cross-sectional TEM views of Intel’s 32nm CMOS devices
P. Packan et al., IEDM Technical Digest, pp , 2009
EE130/230A Fall 2013
Lecture 23, Slide 12

13. Historical Voltage Scaling
Since VT cannot be scaled down aggressively, the supply voltage (VDD) has not been scaled down in proportion to the MOSFET gate length:
VDD
VDD – VT
Source: P. Packan (Intel),
2007 IEDM Short Course
EE130/230A Fall 2013
Lecture 23, Slide 13

14. Power Density Scaling – NOT!
Power Density (W/cm2)
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
1E+01
1E+02
1E+03
0.01
0.1 1
Gate Length (μm)
Passive Power Density
Active Power Density
Source: B. Meyerson (IBM) Semico Conf.,
January 2004
Power Density Trend
Power Density Prediction circa 2000
4004
8008
8080
8085
8086
286
386
486
Pentium® proc P6 1 10
100
1000
10000
1970
1980
1990
2000
2010
Year
Power Density (W/cm2)
Hot Plate
Nuclear Reactor
Rocket Nozzle
Source: S. Borkar (Intel )
Sun’s Surface
EE130/230A Fall 2013
Lecture 23, Slide 14

15. Parallelism
Computing performance is now limited by power dissipation. This has forced the move to parallelism as the principal means of increasing system performance.
Energy vs. Delay per operation
single
core
4004
8008
8080
8085
8086
286
386
486
Pentium® proc P6 1 10
100
1000
10000
1970
1980
1990
2000
2010
Year
Power Density (W/cm2)
Hot Plate
Nuclear Reactor
Rocket Nozzle
Sun’s Surface
dual
core
Operate at a lower energy point (lower VDD)
- CMOS processes keep scaling, but supply voltages & thresholds are not  energy is not scaling
- To keep improving performance without blowing the roof off of the power budget, drop supply & parallelize
Remove gate/Length scaling, simplify
1/throughput
Core 2
Run in parallel to recoup performance
Source: S. Borkar (Intel )
EE130/230A Fall 2013
Lecture 23, Slide 15

16. Key to VDD Reduction: Gate Control
Body
Gate
Drain
log ID
ION
VDD
Cox
Cdep
Source
VGS
The greater the capacitive coupling between Gate and channel, the better control the Gate has over the channel potential.
lower VDD to achieve target ION/IOFF
reduced short-channel effect (SCE) and
drain-induced barrier lowering (DIBL)
EE130/230A Fall 2013
Lecture 23, Slide 16

17. Intel Ivy Bridge Processor
EE130/230A Fall 2013
Lecture 23, Slide 17