Presentation on theme: "Feb. 17, 2011 Midterm overview Real life examples of built chips"— Presentation transcript:
1Feb. 17, 2011 Midterm overview Real life examples of built chips Clock SkewArithmeticData CentersPower reduction techniquesDynamic Voltage / Frequency ScalingClock ThrottlingPower GatingOthers?Project – 4b adder with Razor recovery
7The Mirror AdderThe NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carry- generation circuitry.When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important.The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .The transistors connected to Ci are placed closest to the output.Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.
23Power Reduction Techniques Stop the clockDynamic power reductionPower gatingReduce the leakageHow fast can you turn something on/off?Nothing to do sleepHow can you save power while in operation?Near-threshold design
37DSP Parallelization Clock speed reduced by ½ Intuition? Can parallelize furtherIncrease number of MACs(multiply/accumulates) by 2Intuition?Area goes up by 2Power decreases (clock rate down by 2, computations up by 2, but easier timing constraints)What about clock power?Save a little power, but double the area?
38Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
45Project Description Minimal: 4b Adder, Implemented with Razor Simulations into near-threshold domainGrad. Student: requires more advanced designAnalog: Opamps built using invertersDigital: Adiabatic Near-ThresholdPower Gating: add power gating to your designUndergrad: extra credit if do any of the above
46Problem 1: On-Chip Wires Consume Energy On-chip wire power does not scaleDominated by interconnect capacitance (CVDD2)VDDEb1V150fJ/mmON-CHIP (Status Quo):fJ/bit/mmOn-chip wires start to dominate power consumption, as computational logic energy is minimized when operating in near-threshold. Here is a graph for a recentDOE exascale study, showing that in the next 8 years, the energy to perform a double-precision FLOP will improve by 5x, but on-chip wires will not. For example,1mm and 5mm on-chip links will not have changed, because energy is proportional to capacitance, and fringe capacitance will not improve with technology scaling.Note that from our initial work with near-threshold computation, the amount of energy it takes to perform a 16b multiply/Accumulate is 200fJ for Vdd=0.4V. The amountOf energy to move that 16b parallel bus 300um distance will cost 250fJ – or more energy than it takes to perform computation.Hence, low-Vdd operation accentuates to the problem of energy-consumption within on-chip wires. We will need to propose another 5-10x improvement in energy-efficiency for on-chip wires in order to close this gap when logic operates in near-threshold regime.OUR GOAL: < 5fJ/bit/mmNOTE: Sub/Near-Threshold doesn’t help this problem![DOE, Exascale Workshop]