Presentation on theme: "The scale of IC design Small-scale integrated, SSI: gate number usually less than 10 in a IC. Medium-scale integrated, MSI: gate number ~10-100, can operate."— Presentation transcript:
1The scale of IC designSmall-scale integrated, SSI: gate number usually less than 10 in a IC.Medium-scale integrated, MSI: gate number ~10-100, can operate single andsimple function(such as 4-bit adder).Large-scale integrated, LSI: gate number ~100- few 1000, can operate as aprocessor, memory, and programmable module.4. Very large-scale integrated, VLSI: few 1000-few billions of gates, can operatecomplex micro-processor, digital signal processing.A SSI IC
3Design of circuits with limited gate Fan-in The physical operation of a IC circuit, you will meet issues such asGate delayLimited inputs or outputsWhat is Fan-in and Fan-out?Fan-in: For a electronics device, the gate speed is limited. Therefore, for a singlegate, the inputs is not over 4 or 5. So for a high Fan-in circuit, we will convertit into a multilevel circuit.#Original is 7 Fan-in, convert to 4.2. Fan-out: For a typical gate, having a standard load, for example, a invertor havinga limited one standard load. When the output load is increased , transitiontime will increased. The maximum Fan-out is defined to be the largest loadit can derived.
4Figure 8.1 Design of circuits with limited gate fan-in Example: For a two-level circuit ,you will having : two 4-input gates and one 5-input gate
5Convert to NOR-gate circuit If factoring this function to a multi-level circuit, you will lower the gates inputs:Convert to NOR-gate circuit8-5
6Example: Realize the functions using only two-input NAND gates and invertors. After minimize from each K-mapEach requires a 3-input OR gate
7Step1:We will factor to reducre the number of gate inputs: We will select this expression because it share thecommon gate with f1We need to further reduce the gate input from f3DeMorgen’s
8Figure 8.3 Realization of Figure 8.2 Step2: Convert to a NAND circuitFigure 8.3 Realization of Figure 8.2Because the output gate is OR, we convert to NAND gates circuit
9Figure 8.4 Propagation Delay in an Inverter Gate Delays and Timing DiagramFigure 8.4 Propagation Delay in an InverterThis delay is from the transistor or switchingelements within gate take time to react toa charge in input.2. A Propagation delay : e (~nanoseconed)3. For some type of sequential circuit, even short delays may be important.
14Figure 8.7 Types of Hazards Hazard in combinational logicA unwanted switching transients occurs when different paths from input to output havedifferent propagation delayFigure 8.7 Types of Hazards突波 或是 雜訊靜態 1-雜訊
15Figure 8.8 Detection of a 1-Hazard If A=C=1,B change from 1 to 0Assume each gate delay is 10nsIdeal case:F output always 1But actually, HazardOccurs.This is called aInertial delay!(慣性延遲)0 glitch(失靈)
19Simulation and Testing of logic circuits As logic circuits become more and more complex, it is very important to simulate adesign before actually building it.Simulation is done for several reason:Verify the design is logically correctVerify the timing of logic signalFaulty component
20Figure 8.12 For a simulating logic circuit: 0, 1 , unknown(X), open-circuit(Z, high impedance, hi-Z)Probe each gate output: Help to debug the error.
21Table 8.1 AND and OR Functions for four valued Simulation Debugging: If a circuit output is wrong, this may due to several possible causes:Incorrect designGates connected wrongWrong input signalsDefective gatesDefective connecting wires.If output gate has the wrong output and the input is correct, this indicates theGate is defective.Table 8.1 AND and OR Functions for four valued Simulation
22Figure 8.13 Logic Circuit with Incorrect Output Example: How to do the trouble shorting in this device?A student in lab found that when A=B=C=D=1, the output F is wrong.F= AB(C’D+CD’) + A’B’(C+D)Gate 7 shows that one of the inputs is wrong. (output should be 0)Output of Gate-5 is wrong, it should be 0. So Gate-3 is wrong.Gate-1 And Gate-2 is correct, so input to Gate-3 is correct.So we can find that Gate-3 is defective.