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**Combinational Circuit Design and Simulation Using Gates**

PowerPoint Presentation Combinational Circuit Design and Simulation Using Gates UNIT 8 © Cengage Learning, Engineering. All Rights Reserved. 1-0 ©2010 Cengage Learning Engineering. All Rights Reserved.

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The scale of IC design Small-scale integrated, SSI: gate number usually less than 10 in a IC. Medium-scale integrated, MSI: gate number ~10-100, can operate single and simple function(such as 4-bit adder). Large-scale integrated, LSI: gate number ~100- few 1000, can operate as a processor, memory, and programmable module. 4. Very large-scale integrated, VLSI: few 1000-few billions of gates, can operate complex micro-processor, digital signal processing. A SSI IC

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TLC IC (74系列)

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**Design of circuits with limited gate Fan-in**

The physical operation of a IC circuit, you will meet issues such as Gate delay Limited inputs or outputs What is Fan-in and Fan-out? Fan-in: For a electronics device, the gate speed is limited. Therefore, for a single gate, the inputs is not over 4 or 5. So for a high Fan-in circuit, we will convert it into a multilevel circuit. #Original is 7 Fan-in, convert to 4. 2. Fan-out: For a typical gate, having a standard load, for example, a invertor having a limited one standard load. When the output load is increased , transition time will increased. The maximum Fan-out is defined to be the largest load it can derived.

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**Figure 8.1 Design of circuits with limited gate fan-in Example:**

For a two-level circuit ,you will having : two 4-input gates and one 5-input gate

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**Convert to NOR-gate circuit**

If factoring this function to a multi-level circuit, you will lower the gates inputs: Convert to NOR-gate circuit 8-5

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**Example: Realize the functions using only two-input NAND gates and invertors.**

After minimize from each K-map Each requires a 3-input OR gate

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**Step1:We will factor to reducre the number of gate inputs:**

We will select this expression because it share the common gate with f1 We need to further reduce the gate input from f3 DeMorgen’s

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**Figure 8.3 Realization of Figure 8.2**

Step2: Convert to a NAND circuit Figure 8.3 Realization of Figure 8.2 Because the output gate is OR, we convert to NAND gates circuit

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**Figure 8.4 Propagation Delay in an Inverter**

Gate Delays and Timing Diagram Figure 8.4 Propagation Delay in an Inverter This delay is from the transistor or switching elements within gate take time to react to a charge in input. 2. A Propagation delay : e (~nanoseconed) 3. For some type of sequential circuit, even short delays may be important.

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**A more detail defination**

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A spec. of logic gate

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**Figure 8.5 Timing Diagram for AND-NOR Circuit**

Example: A timing diagram for AND-NOR Circuit Figure 8.5 Timing Diagram for AND-NOR Circuit Assume each gate has a propagation delay of 20 ns ©2010 Cengage Learning Engineering. All Rights Reserved.

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**Figure 8.6 Timing Diagram for Circuit with Delay**

Example: A timing diagram for a Circuit delay Figure 8.6 Timing Diagram for Circuit with Delay Assume each gate has a propagation delay of 2 ms ©2010 Cengage Learning Engineering. All Rights Reserved.

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**Figure 8.7 Types of Hazards**

Hazard in combinational logic A unwanted switching transients occurs when different paths from input to output have different propagation delay Figure 8.7 Types of Hazards 突波 或是 雜訊 靜態 1-雜訊

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**Figure 8.8 Detection of a 1-Hazard**

If A=C=1, B change from 1 to 0 Assume each gate delay is 10ns Ideal case: F output always 1 But actually, Hazard Occurs. This is called a Inertial delay!(慣性延遲) 0 glitch(失靈)

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**Figure 8.9 Circuit with Hazard Removed**

Hazard can be detected using K-map Figure 8.9 Circuit with Hazard Removed ©2010 Cengage Learning Engineering. All Rights Reserved.

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**Figure 8.10 Detection of a Static 0-Hazard**

注意電路AND ourput : POS F= (A+C)(A’+D’)(B’+C’+D) When A=0,B=1,D=0 Then C from 0 to 1. 0-Hazard occurs! ©2010 Cengage Learning Engineering. All Rights Reserved.

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**Figure 8.11 Kanaugh Map Removing Hazards of Figure 8.10**

K-map removing Harzards Figure 8.11 Kanaugh Map Removing Hazards of Figure 8.10 F= (A+C)(A’+D’)(B’+C’+D)(C+D’)(A+B’+D) (A’+B’+C’)

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**Simulation and Testing of logic circuits**

As logic circuits become more and more complex, it is very important to simulate a design before actually building it. Simulation is done for several reason: Verify the design is logically correct Verify the timing of logic signal Faulty component

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**Figure 8.12 For a simulating logic circuit:**

0, 1 , unknown(X), open-circuit(Z, high impedance, hi-Z) Probe each gate output: Help to debug the error.

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**Table 8.1 AND and OR Functions for four valued Simulation**

Debugging: If a circuit output is wrong, this may due to several possible causes: Incorrect design Gates connected wrong Wrong input signals Defective gates Defective connecting wires. If output gate has the wrong output and the input is correct, this indicates the Gate is defective. Table 8.1 AND and OR Functions for four valued Simulation

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**Figure 8.13 Logic Circuit with Incorrect Output**

Example: How to do the trouble shorting in this device? A student in lab found that when A=B=C=D=1, the output F is wrong. F= AB(C’D+CD’) + A’B’(C+D) Gate 7 shows that one of the inputs is wrong. (output should be 0) Output of Gate-5 is wrong, it should be 0. So Gate-3 is wrong. Gate-1 And Gate-2 is correct, so input to Gate-3 is correct. So we can find that Gate-3 is defective.

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HProblem 8.1 Chapter 8 HW ©2010 Cengage Learning Engineering. All Rights Reserved.

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Problem 8.3 ©2010 Cengage Learning Engineering. All Rights Reserved.

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**©2010 Cengage Learning Engineering. All Rights Reserved.**

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**Figure 8.14 Circuit Driving Seven-Segment Module**

©2010 Cengage Learning Engineering. All Rights Reserved.

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K-map Truth table Chip

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Problem 8.N ©2010 Cengage Learning Engineering. All Rights Reserved.

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