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©2010 Cengage Learning Engineering. All Rights Reserved.8-0 Combinational Circuit Design and Simulation Using Gates PowerPoint Presentation © 2010. Cengage.

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Presentation on theme: "©2010 Cengage Learning Engineering. All Rights Reserved.8-0 Combinational Circuit Design and Simulation Using Gates PowerPoint Presentation © 2010. Cengage."— Presentation transcript:

1 ©2010 Cengage Learning Engineering. All Rights Reserved.8-0 Combinational Circuit Design and Simulation Using Gates PowerPoint Presentation © Cengage Learning, Engineering. All Rights Reserved. 1-0 UNIT 8

2 8-1 The scale of IC design 1.Small-scale integrated, SSI: gate number usually less than 10 in a IC. 2.Medium-scale integrated, MSI: gate number ~10-100, can operate single and simple function(such as 4-bit adder). 3.Large-scale integrated, LSI: gate number ~100- few 1000, can operate as a processor, memory, and programmable module. 4. Very large-scale integrated, VLSI: few 1000-few billions of gates, can operate complex micro-processor, digital signal processing. A SSI IC

3 8-2 TLC IC (74 )

4 8-3 Design of circuits with limited gate Fan-in The physical operation of a IC circuit, you will meet issues such as (1)Gate delay (2)Limited inputs or outputs What is Fan-in and Fan-out? 1.Fan-in: For a electronics device, the gate speed is limited. Therefore, for a single gate, the inputs is not over 4 or 5. So for a high Fan-in circuit, we will convert it into a multilevel circuit. #Original is 7 Fan-in, convert to Fan-out: For a typical gate, having a standard load, for example, a invertor having a limited one standard load. When the output load is increased, transition time will increased. The maximum Fan-out is defined to be the largest load it can derived.

5 Figure 8.1 Design of circuits with limited gate fan-in Example: For a two-level circuit,you will having : two 4-input gates and one 5-input gate

6 8-5 Convert to NOR-gate circuit If factoring this function to a multi-level circuit, you will lower the gates inputs:

7 8-6 Example: Realize the functions using only two-input NAND gates and invertors. After minimize from each K-map Each requires a 3-input OR gate

8 8-7 Step1:We will factor to reducre the number of gate inputs: We will select this expression because it share the common gate with f 1 We need to further reduce the gate input from f 3 DeMorgens

9 8-8 Figure 8.3 Realization of Figure 8.2 Because the output gate is OR, we convert to NAND gates circuit Step2: Convert to a NAND circuit

10 8-9 Figure 8.4 Propagation Delay in an Inverter Gate Delays and Timing Diagram 1.This delay is from the transistor or switching elements within gate take time to react to a charge in input. 2. A Propagation delay : nanoseconed For some type of sequential circuit, even short delays may be important.

11 8-10 A more detail defination

12 8-11 A spec. of logic gate

13 ©2010 Cengage Learning Engineering. All Rights Reserved.8-12 Figure 8.5 Timing Diagram for AND-NOR Circuit Example: A timing diagram for AND-NOR Circuit Assume each gate has a propagation delay of 20 ns

14 ©2010 Cengage Learning Engineering. All Rights Reserved.8-13 Figure 8.6 Timing Diagram for Circuit with Delay Example: A timing diagram for a Circuit delay Assume each gate has a propagation delay of 2 s

15 8-14 Figure 8.7 Types of Hazards Hazard in combinational logic A unwanted switching transients occurs when different paths from input to output have different propagation delay 1-

16 8-15 Figure 8.8 Detection of a 1- Hazard If A=C=1, B change from 1 to 0 Assume each gate delay is 10ns 1 1 Ideal case: F output always 1 But actually, Hazard Occurs. This is called a Inertial delay!( ) 0 glitch( )

17 ©2010 Cengage Learning Engineering. All Rights Reserved.8-16 Figure 8.9 Circuit with Hazard Removed Hazard can be detected using K-map

18 ©2010 Cengage Learning Engineering. All Rights Reserved.8-17 Figure 8.10 Detection of a Static 0-Hazard AND ourput : POS F= (A+C)(A+D)(B+C+D) When A=0,B=1,D=0 Then C from 0 to 1. 0-Hazard occurs!

19 8-18 Figure 8.11 Kanaugh Map Removing Hazards of Figure 8.10 K-map removing Harzards F= (A+C)(A+D)(B+C+D)(C+D)(A+B+D) (A+B+C)

20 8-19 Simulation and Testing of logic circuits As logic circuits become more and more complex, it is very important to simulate a design before actually building it. Simulation is done for several reason: 1.Verify the design is logically correct 2.Verify the timing of logic signal 3.Faulty component

21 8-20 Figure 8.12 For a simulating logic circuit: 1.0, 1, unknown(X), open-circuit(Z, high impedance, hi-Z) 2.Probe each gate output: Help to debug the error.

22 8-21 Table 8.1 AND and OR Functions for four valued Simulation Debugging: If a circuit output is wrong, this may due to several possible causes: 1.Incorrect design 2.Gates connected wrong 3.Wrong input signals 4.Defective gates 5.Defective connecting wires. If output gate has the wrong output and the input is correct, this indicates the Gate is defective.

23 8-22 Figure 8.13 Logic Circuit with Incorrect Output Example: How to do the trouble shorting in this device? A student in lab found that when A=B=C=D=1, the output F is wrong. F= AB(CD+CD) + AB(C+D) 1.Gate 7 shows that one of the inputs is wrong. (output should be 0) 2.Output of Gate-5 is wrong, it should be 0. So Gate-3 is wrong. 3.Gate-1 And Gate-2 is correct, so input to Gate-3 is correct. 4.So we can find that Gate-3 is defective.

24 ©2010 Cengage Learning Engineering. All Rights Reserved.8-23 HProblem 8.1 Chapter 8 HW

25 ©2010 Cengage Learning Engineering. All Rights Reserved.8-24 Problem 8.3

26 ©2010 Cengage Learning Engineering. All Rights Reserved.8-25

27 ©2010 Cengage Learning Engineering. All Rights Reserved.8-26 Figure 8.14 Circuit Driving Seven-Segment Module

28 8-27 K-map Truth table Chip

29 ©2010 Cengage Learning Engineering. All Rights Reserved.8-28 Problem 8.N


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