Download presentation

1
**Exclusive-OR and Exclusive-NOR Gates**

Chapter 6 Exclusive-OR and Exclusive-NOR Gates 1

2
**6-1 The Exclusive-OR Gate**

The output is HIGH if either one or the other inputs are HIGH, but not both. 4

3
The Exclusive-OR Gate Logic circuits for the exclusive-OR function. Logic Symbol and Boolean equation 5

4
**Figure 6-2 The Exclusive-OR Gate built with an AND-OR-NAND combination**

5
**6-2 The Exclusive-NOR Gate**

The complement of the exclusive-OR. Often called an equality gate: The output is HIGH when the inputs are equal (both high or both low). 7

6
**The Exclusive-NOR Gate**

Ex-NOR Logic Circuit EX-NOR Logic Symbol and Boolean equation 8

10
**6-3 Parity Generator / Checker**

Electrical noise in the transmission of binary information can cause errors. 0101 -> 0100 (the electrical noise present on the line during the transmission of the LSB may change 1 to 0) Parity can detect these types of errors. Receiving device can signal an error condition or ask the transmitting device to retransmit. the electrical noise present on the line during the transmission of the LSB may change 1 to 0 At transmitting side 10

11
**Parity systems Adds a bit to the binary information Odd parity systems**

4-bit system requires a 5th bit, an 8-bit system needs a 9th bit. Odd parity systems The parity bit that is added must make the sum of all bits odd. Even parity systems The parity bit that is added must make the sum of all bits even.

12
**Parity systems Parity generator Parity checker**

the circuit that creates the parity bit Parity checker Determines if the received string is of the right parity on the receiving end The type of parity system and the location of parity bit (next to MSB or LSM) must be agreed on beforehand.

13
**Odd parity generator/checker**

This scheme only detects errors that occur to 1 bit. The likelihood of 2 bits being affected is highly unusual. 11

14
**Four-bit even- and odd-parity generators**

12

15
**Eight-bit even-parity generator**

13

16
**Five bit even-parity checker**

14

17
**Integrated-Circuit Parity Generator/Checker**

74280 TTL IC logic symbol and Function Table 15

18
**Parity-Error Detection System**

8-bit even-parity computer configuration. SumE is HIGH if the sum is even. The generated parity bit should be taken from the Odd output because we want the sum of all 9 bits send out to be EVEN. Low means no error, So the Odd output of the checker at the receiver side is used. 17

19
**Parallel Binary Comparator**

1 -> match (two input string are exactly equal)

20
Controlled Inverter Complement an entire string by some control signal. 19

21
Discussion Point Does the circuit below function as an even or odd parity generator? xor 1 = 0 0nxor 0 = 1 Odd parity generator 21

22
Summary The exclusive-OR gate provides a HIGH output if one input or the other input, but not both, is HIGH. The exclusive-NOR gate outputs a HIGH if both inputs are HIGH or if both inputs are LOW. 24

23
Summary A parity bit is commonly used for error detection during the transmission of digital signals. Exclusive-OR and exclusive-NOR gates are used in applications such as parity checking, binary comparison and controlled complementing circuits. FPGAs can be used to implement circuits containing the exclusive gates. 25

Similar presentations

OK

ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices XOR and parity check Circuits.

ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices XOR and parity check Circuits.

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Esi ms ppt online Free ppt on natural disasters Ppt on resistance temperature detector failures Vector scan display ppt online Ppt on asymptotic notation of algorithms definition Ppt on retail marketing mix Ppt on sanskritization definition Ppt on data handling for class 7th Ppt on reliance mutual fund Ppt on leverages synonym