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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 1 Who needs to take EE 40: EECS majors and those transferring into EECS. EECS Minors may take EE 100 or EE 42 with Physics 7b. Bioengineers may take EE 100. EE 100: Basic electrical science, more depth than EE 40 including AC analysis. Very little digital/logic. EE 42: Almost a twin of EE 40. More review of basic Circuit analysis (Physics 7b not assumed). Skips complicated circuits at the end of EE 40. No lab. EE 100: MW 4-5:30, PoolaEE 42: MW 3-4, Oldham

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 2 TYPO-FREE GUARANTEE Every significant typo in lecture or homework (one that changes the answer of the example/problem) results in a bonus point on that weeks homework. 4 points this week! This weeks homework deadline extended to Tuesday, September 10 because of typo. Download correction.

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 3 Lecture 3 Last Time: Logic Gates Synthesis using NAND gates and Sum-of-Products Gate Delays – unit gate delay concept (to be reviewed) Synchronous and Asynchronous Logic (to be reviewed) This Time: Review of Gate Delays Source of Gate Delays Typical waveforms

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 4 UNIT GATE DELAY D (review) Time delay D occurs between input and output: computation is not instantaneous Value of input at t = 0 + determines value of output at later time t = D A B C 0 1 1 0 Logic State t t D 0 0 Input (A and B tied together) Idealized Output

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 5 WHAT IS THE ORIGIN OF GATE DELAY? Logic gates are electronic circuits that process electrical signals Most common signal for logic variable: voltage Specific voltage ranges correspond to 0 or 1 Note that the specific voltage range for 0 or 1 depends on logic family, and in general decreases with logic generations Key Idea: Voltages in real circuits cannot suddenly jump – they actually must change with finite slope. Basic reason: Every node in a circuit has a capacitance to other nodes. Voltages on capacitances cannot jump – that would require transfer of energy in zero time. We will just accept this for now, but examine it more carefully in Lecture 4. Typically, voltages approach their final values asymptotically.

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 6 http://www.interfacebus.com/voltage_threshold.html

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 7 VOLTAGE WAVEFORMS (TIME FUNCTIONS) Inverter input is v IN (t), output is v OUT (t) inside a large system t V in (t) output

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 8 GATE DELAY (PROPAGATION DELAY) Define as the delay required for the output voltage to reach 50% of its final value (this is 0.7 of the traditional exponential decay time constant). Inverters are designed so that the gate delay is symmetrical (rise and fall) V in (t) t 1.5 V out (t) t 1.5 Approximation

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 9 GATE DELAY EXAMPLE Cascade of Logic Gates A B C D Inputs have different delays, but we ascribe a single worst-case delay to every gate How many gate delays for shortest path? How many gate delays for longest path? ANSWER : 2 ANSWER : 3

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 10 D t t t t t Logic state 2 2 0 3 TIMING DIAGRAM FROM LAST TIME Show transitions of variables vs time A B C Note that becomes valid two gate delays after B&C switch, because the invert function takes one delay and the NAND function a second. No change at t = 3 Note becomes valid one gate delay after B switches 1 0

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 11 D t t t t t Logic state 2 2 0 3 TIMING DIAGRAM WITH ONE CHANGE (Change output gate to NOR from NAND) A B C Note that becomes valid two gate delays after B&C switch, because the invert function takes one delay and the NAND function a second. Note becomes valid one gate delay after B switches 1 0 False change of D at t = 2

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 12 D t t t t Logic state 2 2 0 3 TIMING DIAGRAM WITH ONE MORE CHANGE (Insert AND function at output – CLOCK) Output will always be zero until a gate delay after K goes high A B C False change of D at t = 2 need not disturb the output F, if we keep K low until t = 3 and then bring K high. 1 0 This is one way to get an asynchronous logic function. K F Note that intermediate results are unchanged

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 13 EFFECT OF PROPAGATION DELAY ON PROCESSOR SPEED Computer architects would like each system clock cycle to have between 20 and 50 gate delays … use 35 for calculations Implication: clock frequency = 500 MHz clock period = (5 10 8 s 1 ) 1 Period = 2 10 9 s = 2 ns (nanoseconds) Gate delay must be = (1/35) Period = (2 ns)/35 = 57 ps (picoseconds) How fast is this? Speed of light: c = 3 10 8 m/s (~1ns per foot) Distance traveled in 57 ps is: C X = (3x10 8 m/s)(57x10 -12s ) = 17 x 10 -4 m = 1.7cm

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 14 WHAT DETERMINES GATE DELAY? The delay is mostly simply the charging of the capacitors at internal nodes. We need to learn the fundamentals of electronic circuits to analyze this. charge, current, voltage, power, circuit elements such as sources, resistors, etc (Physics 7B) … Lecture 4 reviews these basic quantities needed for electrical circuit calculations Lecture 5 calculates delays owing to charging of capacitors.

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 15 Example from Lecture 5 The gate delay is simply the charging of the capacitors at internal nodes. R C R = 1000, C= 10 -13 F t v IN 2.5 5 V OUT For these R and C values the delay encountered (using our criterion of half way) is 69 ps. We will see how this is calculated in the next lecture. = 0.069ns

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 16 Review of charging and discharging in RC Circuits (an enlightened approach) Before we continue with formal circuit analysis - lets review RC circuits Rationale: Every node in a circuit has capacitance to ground, like it or not, and its the charging of these capacitances that limits real circuit performance (speed) Relevance to digital circuits: We communicate with pulses We send beautiful pulses out But we receive lousy-looking pulses and must restore them RC charging effects are responsible …. So lets review them.

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 17 Example from earliest days of digital circuits: The first transatlantic telegraph Remember - the code was dots and dashes The input pulse for a dot was about a tenth second long and a large voltage The details of the distortion mechanism involve transmission-line theory something we can better understand after we first take on simple RC circuits, but to really treat correctly, we need to study Electromagnetic Theory (EECS 117A). What emerged at the other end was an attenuated pulse about 3 seconds long!

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 18 What environment do pulses face? Every wire in a circuit has resistance. Every junction (called nodes) has capacitance to ground and other nodes. The active circuit elements (transistors) add additional resistance in series with the wires, and additional capacitance in parallel with the node capacitance. A pulse originating at node I will arrive delayed and distorted at node O because it takes time to charge C through R I O

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 19 Why study RC circuits now (before even basic circuit analysis)? Motivation: Understand the degradation of digital signals and the need for regeneration. Approach: pick the simplest basic circuit (one R and one C) and really understand it (lets totally beat it up!) Background: In high school and college physics we already studied resistors and capacitors More background: In calculus and differential equations we already solved the only differential equation we will see all semester. More background: We know from math that for linear differential equations there is a unique solution, so no matter how we find it, if it satisfies the equation and boundary conditions it is the one and only true solution. Icing: Heck, we have all seen decaying exponentials before, so we all we have to do is just make much closer friends of them.

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W. G. Oldham EECS 40 Fall 2001 Lecture 3 Copyright Regents of University of California 20 An example of the kind of circuit we will deal with in weeks 10-15 Note that its just a bunch of Rs and Cs. It will be easy!

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