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**Morgan Kaufmann Publishers**

11 April, 2017 Universal Gates Chapter 4 — The Processor

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**Outline Universal Gates : NAND and NOR NAND Gate NOR Gate**

Implementation using NAND Gates Implementation using NOR Gates

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**Outline Universal Gates : NAND and NOR NAND Gate NOR Gate**

Implementation using NAND Gates Implementation using NOR Gates

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**Universal Gates: NAND and NOR**

AND/OR/NOT gates are sufficient for building any Boolean functions. We call the set {AND, OR, NOT} a complete set of logic. However, other gates are also used because: (i) usefulness (ii) economical on transistors (iii) self-sufficient NAND/NOR: economical, self-sufficient XOR: useful (e.g. parity bit generation)

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**(x.x)' = x' (T1: idempotency)**

NAND Gate (1/2) NAND gate is self-sufficient (can build any logic circuit with it). Therefore, {NAND} is also a complete set of logic. Can be used to implement AND/OR/NOT. Implementing an inverter using NAND gate: x x' (x.x)' = x' (T1: idempotency)

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**NAND Gate (2/2) Implementing AND using NAND gates:**

x x.y y (x.y)' ((x.y)'(x.y)')' = ((x.y)')' idempotency = (xy) involution Implementing OR using NAND gates: x x+y y x' y' ((x.x)'(y.y)')' = (x'.y')' idempotency = x''+y'' DeMorgan = x+y involution

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**(x+x)' = x' (T1: idempotency)**

NOR Gate (1/2) NOR gate is also self-sufficient. Therefore, {NOR} is also a complete set of logic Can be used to implement AND/OR/NOT. Implementing an inverter using NOR gate: x x' (x+x)' = x' (T1: idempotency)

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**NOR Gate (2/2) Implementing AND using NOR gates:**

x x.y y x' y' ((x+x)'+(y+y)')'=(x'+y')' idempotency = x''.y'' DeMorgan = x.y involution Implementing OR using NOR gates: x x+y y (x+y)' ((x+y)'+(x+y)')' = ((x+y)')' idempotency = (x+y) involution

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**Outline Universal Gates : NAND and NOR NAND Gate NOR Gate**

Implementation using NAND Gates Implementation using NOR Gates

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**Implementation using NAND gates (1/2)**

Possible to implement any Boolean expression using NAND gates. Procedure: (i) Obtain sum-of-products Boolean expression: Example: F3 = x.y'+x'.z (ii) Use DeMorgan theorem to obtain expression using 2-level NAND gates = (x.y'+x'.z)' ' involution = ((x.y')' . (x'.z)')' DeMorgan

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**Implementation using NAND gates (2/2)**

x' z F3 (x'.z)' (x.y')' x y' F3 = ((x.y')'.(x'.z)') ' = x.y' + x'.z

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**Outline Universal Gates : NAND and NOR NAND Gate NOR Gate**

Implementation using NAND Gates Implementation using NOR Gates

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**Implementation using NOR gates (1/2)**

Possible to implement any Boolean expression using NOR gates. Procedure: (i) Obtain product-of-sums Boolean expression: Example: F6 = (x+y').(x'+z) (ii) Use DeMorgan theorem to obtain expression using 2-level NOR gates. = ((x+y').(x'+z))' ' involution = ((x+y')'+(x'+z)')' DeMorgan

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**Implementation using NOR gates (2/2)**

x' z F6 (x'+z)' (x+y')' x y' F6 = ((x+y')'+(x'+z)')' = (x+y').(x'+z)

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Chapter 2 Two- Level Combinational Logic. Chapter Overview Logic Functions and Switches Not, AND, OR, NAND, NOR, XOR, XNOR Gate Logic Laws and Theorems.

Chapter 2 Two- Level Combinational Logic. Chapter Overview Logic Functions and Switches Not, AND, OR, NAND, NOR, XOR, XNOR Gate Logic Laws and Theorems.

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