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**Power and Energy Basics**

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Chapter Outline Metrics Dynamic power Static power Energy-delay trade-off’s

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**Metrics Delay (sec): Energy (Joule) Power (Watt) Power*Delay (Joule)**

Performance metric Energy (Joule) Efficiency metric: effort to perform a task Power (Watt) Energy consumed per unit time Power*Delay (Joule) Mostly a technology parameter – measures the efficiency of performing an operation in a given technology Energy*Delay = Power*Delay2 (Joule-sec) Combined performance and energy metric – figure of merit of design style Other Metrics: Energy-Delayn (Joule-secn) Increased weight on performance over energy

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**Where is Power Dissipated in CMOS?**

Active (Dynamic) power (Dis)charging capacitors Short-circuit power Both pull-up and pull-down on during transition Static (leakage) power Transistors are imperfect switches Static currents Biasing currents

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**Active (or Dynamic) Power**

Key property of active power: with f the switching frequency Sources: Charging and discharging capacitors Temporary glitches (dynamic hazards) Short-circuit currents

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**Charging Capacitors Applying a voltage step R V C**

Value of R does not impact energy!

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**Applied to Complementary CMOS Gate**

V dd PMOS i L A NETWORK 1 V out A N C NMOS L NETWORK One half of the power from the supply is consumed in the pull-up network and one half is stored on CL Charge from CL is dumped during the 10 transition Independent of resistance of charging/discharging network

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**Circuits with Reduced Swing**

Energy consumed is proportional to output swing

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**Charging Capacitors - Revisited**

Driving from a constant current source R I C Energy dissipated in resistor can be reduced by increasing charging time T (that is, decreasing I)

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**Charging Capacitors Using constant voltage or current driver?**

Econstant_current < Econstant_voltage if T > 2RC Energy dissipated using constant current charging can be made arbitrarily small at the expense of delay: Adiabatic charging Note: tp(RC) = 0.69 RC t0→90%(RC) = 2.3 RC

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Charging Capacitors Driving using a sine wave (e.g. from resonant circuit) R v(t) C Energy dissipated in resistor can be made arbitrarily small if frequency w << 1/RC (output signal in phase with input sinusoid)

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**Dynamic Power Consumption**

Power = Energy/transition • Transition rate = CLVDD2 • f01 = CLVDD2 • f • P01 = CswitchedVDD2 • f Power dissipation is data dependent – depends on the switching probability Switched capacitance Cswitched = P01CL= a CL (a is called the switching activity)

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**Impact of Logic Function**

Example: Static 2-input NOR gate Assume signal probabilities pA=1 = 1/2 pB=1 = 1/2 A B Out 1 Then transition probability p01 = pOut=0 x pOut=1 = 3/4 x 1/4 = 3/16 If inputs switch every cycle aNOR = 3/16 NAND gate yields similar result

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**Impact of Logic Function**

Example: Static 2-input XOR Gate Assume signal probabilities pA=1 = 1/2 pB=1 = 1/2 A B Out 1 Then transition probability p01 = pOut=0 x pOut=1 = 1/2 x 1/2 = 1/4 Assumes inputs of 0 and 1 are equally likely. For dynamic gates, the activity depends only on the signal probability - while for the static case the transition probability depends on the previous state. Remember for static NOR gate P0->1 = 3/16 If inputs switch in every cycle P01 = 1/4

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**Transition Probabilities for Basic Gates**

As a function of the input probabilities p01 AND (1 - pApB)pApB OR (1 - pA)(1 - pB)(1 - (1 - pA)(1 - pB)) XOR (1 - (pA +pB – 2pApB))(pA + pB – 2pApB) Activity for static CMOS gates a = p0p1

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**Activity as a Function of Topology**

XOR versus NAND/NOR XOR NAND/NOR aNOR,NAND = (2N-1)/22N aXOR = 1/4

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**How about Dynamic Logic?**

VDD Eval Precharge Energy dissipated when effective output is zero! or P0→1 = P0 Always larger than P0P1! E.g. P0→1(NAND) = 1/2N ; P0→1(NOR) = (2N-1)/2N Activity in dynamic circuits hence always higher than static. But … capacitance most often smaller.

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**Transition probability is 1!**

Differential Logic? VDD Static: Activity is doubled Dynamic: Transition probability is 1! Out Out Gate Hence: power always increases.

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**Evaluating Power Dissipation of Complex Logic**

Simple idea: start from inputs and propagate signal probabilities to outputs P1 But: Reconvergent fanout Feedback and temporal/spatial correlations

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**Reconvergent Fanout (Spatial Correlation)**

Inputs to gate can be interdependent (correlated) reconvergence no reconvergence reconvergent PZ = 1-(1-PA)PB PZ = 1-(1-PA)PA ? NO! PZ = 1 PZ: probability that Z=1 Must use conditional probabilities PZ = 1- PA . P(X|A) = 1 probability that X=1 given that A=1 Becomes complex and intractable real fast

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**Temporal Correlations**

Feedback Temporal correlation in input streams R Logic X … … Both streams have same P = 1 but different switching statistics X is a function of itself → correlated in time Activity estimation the hardest part of power analysis Typically done through simulation with actual input vectors (see later)

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**Glitching in Static CMOS**

Analysis so far did not include timing effects ABC 101 000 X Glitch Z Gate Delay Also known as dynamic hazards: “A single input change causing multiple changes in the output” The result is correct, but extra power is dissipated

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**Example: Chain of NAND Gates**

1 Out 2 3 4 5 200 400 600 0.0 1.0 2.0 3.0 Time (ps) 8 6 7 Voltage (V)

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What Causes Glitches? A,B A,B C,D X Y Z C,D X Y Z Uneven arrival times of input signals of gate due to unbalanced delay paths Solution: balancing delay paths!

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**Short-Circuit Currents**

(also called crowbar currents) PMOS and NMOS simultaneously on during transition Psc ~ f

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**Short-Circuit Currents**

V in out C L DD I sc = MAX V in out C L DD I sc ~ time (s) 20 - 0.5 1 1.5 2 2.5 40 60 Isc (A) x 10 4 C L = 20 fF = 100 fF = 500 fF Large load Small load Equalizing rise/fall times of input and output signals limits Psc to 10-15% of the dynamic dissipation [Ref: H. Veendrick, JSSC’84]

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**Modeling Short-Circuit Power**

Can be modeled as capacitor a, b: technology parameters k: function of supply and threshold voltages, and transistor sizes Easily included in timing and power models

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**Transistors Leak Drain leakage Junction leakages Gate leakage**

Diffusion currents Drain-induced barrier lowering (DIBL) Junction leakages Gate-induced drain leakage (GIDL) Gate leakage Tunneling currents through thin oxide

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**Sub-threshold Leakage**

Off-current increases exponentially when reducing VTH Pleak = VDD.Ileak

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**Sub-Threshold Leakage**

Leakage current increases with drain voltage (mostly due to DIBL) (for VDS > 3 kT/q) Hence Leakage Power strong function of supply voltage

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**Stack Effect NAND gate: VDD**

Assume that body effect in short channel transistor is small NAND gate: VDD (instead of the expected factor of 2)

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**Stack Effect IM1 IM2 factor 9 90 nm NMOS Leakage Reduction 2 NMOS 9**

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.5 2 2.5 3 x 10 -9 V M (V) Ileak (A) IM1 IM2 90 nm NMOS factor 9 Leakage Reduction 2 NMOS 9 3 NMOS 17 4 NMOS 24 2 PMOS 8 3 PMOS 12 4 PMOS 16

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**Gate Tunneling Exponential function of supply voltage**

DD 0V I SUB GD GS Leak Exponential function of supply voltage IGD~ e-ToxeVGD, IGS~ e-ToxeVGS Independent of the sub-threshold leakage 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.2 1.4 1.6 1.8 x 10 -10 VDD (V) Igate (A) 90 nm CMOS Modeled in BSIM4 Also in BSIM3v3 (but not always included in foundry models) NMOS gate leakage usually worse than PMOS

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**Other sources of static power dissipation**

Diode (drain-substrate) reverse bias currents p+ n+ n+ p+ p+ n+ n well p substrate Electron-hole pair generation in depletion region of reverse-biased diodes Diffusion of minority carriers through junction For sub-50nm technologies with highly-doped pn junctions, tunneling through narrow depletion region becomes an issue Strong function of temperature Much smaller than other leakage components in general

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**Other sources of static power dissipation**

Circuit with dc bias currents: sense amplifiers, voltage converters and regulators, sensors, mixed-signal components, etc Should be turned off if not used, or standby current should be minimized

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**Summary of Power Dissipation Sources**

a – switching activity CL – load capacitance CCS – short-circuit capacitance Vswing – voltage swing f – frequency IDC – static current Ileak – leakage current

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**The Traditional Design Philosophy**

Maximum performance is primary goal Minimum delay at circuit level Architecture implements the required function with target throughput, latency Performance achieved through optimum sizing, logic mapping, architectural transformations. Supplies, thresholds set to achieve maximum performance, subject to reliability constraints

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**CMOS Performance Optimization**

Sizing: Optimal performance with equal fanout per stage Extendable to general logic cone through ‘logical effort’ Equal effective fanouts (giCi+1/Ci) per stage Example: memory decoder [Ref: I. Sutherland, Morgan-Kaufman‘98]

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**Model not Appropriate Any Longer**

Traditional scaling model Maintaining the frequency scaling model While slowing down voltage scaling

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**The New Design Philosophy**

Maximum performance (in terms of propagation delay) is too power-hungry, and/or not even practically achievable Many (if not most) applications either can tolerate larger latency, or can live with lower than maximum clock-speeds Excess performance (as offered by technology) to be used for energy/power reduction Trading off speed for power

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**Relationship Between Power and Delay**

1 2 3 4 -0. 0.4 0.8 0.2 0.6 x 10 -4 VTH (V) VDD Power (W) A B 1 2 3 4 -0.4 0.4 0.8 5 x 10 -10 Delay (s) VTH (V) VDD A B For a given activity level, power is reduced while delay is unchanged if both VDD and VTH are lowered such as from A to B. [Ref: T. Sakurai and T. Kuroda, numerous references]

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**The Energy-Delay Space**

Equal performance curves VDD Equal energy curves VTH Energy minimum

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**Energy-Delay Product as a Metric**

3.5 3 delay 90 nm technology VTH approx 0.35V 2.5 2 1.5 energy-delay 1 energy 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 V DD Energy-delay exhibits minimum at approximately 2 VTH (typical unless leakage dominates)

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**Exploring the Energy-Delay Space**

Unoptimized design Emax Pareto-optimal designs Emin Dmin Dmax Delay In energy-constrained world, design is trade-off process Minimize energy for a given performance requirement Maximize performance for given energy budget [Ref: D. Markovic, JSSC’04]

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**Summary Power and energy are now primary design constraints**

Active power still dominating for most applications Supply voltage, activity and capacitance the key parameters Leakage becomes major factor in sub-100nm technology nodes Mostly impacted by supply and threshold voltages Design has become energy-delay trade-off exercise!

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References D. Markovic, V. Stojanovic, B. Nikolic, M.A. Horowitz, R.W. Brodersen, “Methods for True Energy-Performance Optimization,” IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp , Aug J. Rabaey, A. Chandrakasan, B. Nikolic, “Digital Integrated Circuits: A Design Perspective,” 2nd ed, Prentice Hall 2003. Takayasu Sakurai, ”Perspectives on power-aware electronics,” Digest of Technical Papers ISSCC, pp. 26-29, Febr. 03. I. Sutherland, B. Sproull, and D. Harris, “Logical Effort”, Morgan Kaufmann, 1999. H. Veendrick, “Short-Circuit Dissipation of Static CMOS Circuitry and its Impact on the Design of Buffer Circuits,” IEEE Journal of Solid-State Circuits, Vol. SC-19, no. 4, pp.468–473, 1984.

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Fig. 13.2 Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.

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