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Jan M. Rabaey Low Power Design Essentials ©2008 Chapter 3 Power and Energy Basics

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Low Power Design Essentials ©2008 3.2 Chapter Outline Metrics Dynamic power Static power Energy-delay trade-offs

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Low Power Design Essentials ©2008 3.3 Metrics Delay (sec): –Performance metric Energy (Joule) –Efficiency metric: effort to perform a task Power (Watt) –Energy consumed per unit time Power*Delay (Joule) –Mostly a technology parameter – measures the efficiency of performing an operation in a given technology Energy*Delay = Power*Delay 2 (Joule-sec) –Combined performance and energy metric – figure of merit of design style Other Metrics: Energy-Delay n (Joule-sec n ) –Increased weight on performance over energy

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Low Power Design Essentials ©2008 3.4 Where is Power Dissipated in CMOS? Active (Dynamic) power –(Dis)charging capacitors –Short-circuit power Both pull-up and pull-down on during transition Static (leakage) power –Transistors are imperfect switches Static currents –Biasing currents

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Low Power Design Essentials ©2008 3.5 Active (or Dynamic) Power Sources: Charging and discharging capacitors Temporary glitches (dynamic hazards) Short-circuit currents Key property of active power: with f the switching frequency

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Low Power Design Essentials ©2008 3.6 Charging Capacitors R C V Applying a voltage step Value of R does not impact energy!

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Low Power Design Essentials ©2008 3.7 Applied to Complementary CMOS Gate One half of the power from the supply is consumed in the pull-up network and one half is stored on C L Charge from C L is dumped during the 1 0 transition Independent of resistance of charging/discharging network V dd V out i L C L PMOS NETWORK NMOS A 1 A N NETWORK

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Low Power Design Essentials ©2008 3.8 Circuits with Reduced Swing Energy consumed is proportional to output swing

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Low Power Design Essentials ©2008 3.9 Charging Capacitors - Revisited R C I Driving from a constant current source Energy dissipated in resistor can be reduced by increasing charging time T (that is, decreasing I)

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Low Power Design Essentials ©2008 3.10 Charging Capacitors Using constant voltage or current driver? Energy dissipated using constant current charging can be made arbitrarily small at the expense of delay: Adiabatic charging E constant_current < E constant_voltage if T > 2RC Note: t p (RC) = 0.69 RC t 090% (RC) = 2.3 RC

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Low Power Design Essentials ©2008 3.11 Charging Capacitors Driving using a sine wave (e.g. from resonant circuit) Energy dissipated in resistor can be made arbitrarily small if frequency << 1/RC (output signal in phase with input sinusoid) R C v(t)

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Low Power Design Essentials ©2008 3.12 Dynamic Power Consumption Power = Energy/transition Transition rate = C L V DD 2 f 0 1 = C L V DD 2 f P 0 1 = C switched V DD 2 f Power dissipation is data dependent – depends on the switching probability Switched capacitance C switched = P 0 1 C L = C L ( is called the switching activity)

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Low Power Design Essentials ©2008 3.13 Impact of Logic Function ABOut 001 010 100 110 Example: Static 2-input NOR gate Assume signal probabilities p A=1 = 1/2 p B=1 = 1/2 Then transition probability p 0 1 = p Out=0 x p Out=1 = 3/4 x 1/4 = 3/16 NOR = 3/16 If inputs switch every cycle NAND gate yields similar result

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Low Power Design Essentials ©2008 3.14 Impact of Logic Function ABOut 000 011 101 110 Example: Static 2-input XOR Gate Assume signal probabilities p A=1 = 1/2 p B=1 = 1/2 Then transition probability p 0 1 = p Out=0 x p Out=1 = 1/2 x 1/2 = 1/4 P 0 1 = 1/4 If inputs switch in every cycle

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Low Power Design Essentials ©2008 3.15 Transition Probabilities for Basic Gates p 0 1 AND(1 - p A p B )p A p B OR(1 - p A )(1 - p B )(1 - (1 - p A )(1 - p B )) XOR(1 - (p A +p B – 2p A p B ))(p A + p B – 2p A p B ) Activity for static CMOS gates = p 0 p 1 As a function of the input probabilities

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Low Power Design Essentials ©2008 3.16 Activity as a Function of Topology NOR,NAND = (2 N -1)/2 2N XOR = 1/4 XOR versus NAND/NOR XOR NAND/NOR

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Low Power Design Essentials ©2008 3.17 How about Dynamic Logic? Energy dissipated when effective output is zero! or P 01 = P 0 V DD Eval Precharge Always larger than P 0 P 1 ! Activity in dynamic circuits hence always higher than static. But … capacitance most often smaller. E.g. P 01 (NAND) = 1/2 N ; P 01 (NOR) = (2 N -1)/2 N

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Low Power Design Essentials ©2008 3.18 Differential Logic? V DD Out Gate Static: Activity is doubled Dynamic: Transition probability is 1! Hence: power always increases.

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Low Power Design Essentials ©2008 3.19 Evaluating Power Dissipation of Complex Logic Simple idea: start from inputs and propagate signal probabilities to outputs But: –Reconvergent fanout –Feedback and temporal/spatial correlations P1P1

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Low Power Design Essentials ©2008 3.20 Reconvergent Fanout (Spatial Correlation) P Z = 1- P A. P(X|A) = 1 Becomes complex and intractable real fast Inputs to gate can be interdependent (correlated) no reconvergence P Z = 1-(1-P A )P B reconvergent P Z = 1-(1-P A )P A ? NO! P Z = 1 reconvergence Must use conditional probabilities P Z : probability that Z=1 probability that X=1 given that A=1

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Low Power Design Essentials ©2008 3.21 Temporal Correlations Activity estimation the hardest part of power analysis Typically done through simulation with actual input vectors (see later) R Logic X Feedback X is a function of itself correlated in time Temporal correlation in input streams 01010101010101… 00000001111111… Both streams have same P = 1 but different switching statistics

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Low Power Design Essentials ©2008 3.22 Glitching in Static CMOS ABC101000 X Z Gate Delay The result is correct, but extra power is dissipated Glitch Analysis so far did not include timing effects Also known as dynamic hazards: A single input change causing multiple changes in the output Also known as dynamic hazards: A single input change causing multiple changes in the output

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Low Power Design Essentials ©2008 3.23 Example: Chain of NAND Gates Voltage (V)

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Low Power Design Essentials ©2008 3.24 What Causes Glitches? A,B C,D X Y Z A,B C,D X Y Z Uneven arrival times of input signals of gate due to unbalanced delay paths Solution: balancing delay paths!

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Low Power Design Essentials ©2008 3.25 Short-Circuit Currents (also called crowbar currents) PMOS and NMOS simultaneously on during transition P sc ~ f

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Low Power Design Essentials ©2008 3.26 Short-Circuit Currents Equalizing rise/fall times of input and output signals limits P sc to 10-15% of the dynamic dissipation Large load Small load V in V out C L V DD I sc 0 V in V out C L V DD I sc I MAX time (s) 020 0.5 0 1 1.5 2 2.5 4060 I sc (A) x 10 4 C L = 20 fF C L = 100 fF C L = 500 fF [Ref: H. Veendrick, JSSC84]

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Low Power Design Essentials ©2008 3.27 Modeling Short-Circuit Power Can be modeled as capacitor a, b: technology parameters k: function of supply and threshold voltages, and transistor sizes Easily included in timing and power models

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Low Power Design Essentials ©2008 3.28 Transistors Leak Drain leakage –Diffusion currents –Drain-induced barrier lowering (DIBL) Junction leakages –Gate-induced drain leakage (GIDL) Gate leakage –Tunneling currents through thin oxide

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Low Power Design Essentials ©2008 3.29 Sub-threshold Leakage Off-current increases exponentially when reducing V TH P leak = V DD.I leak

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Low Power Design Essentials ©2008 3.30 Sub-Threshold Leakage Leakage current increases with drain voltage (mostly due to DIBL) (for V DS > 3 kT/q) Hence Leakage Power strong function of supply voltage

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Low Power Design Essentials ©2008 3.31 Stack Effect NAND gate: Assume that body effect in short channel transistor is small (instead of the expected factor of 2) V DD

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Low Power Design Essentials ©2008 3.32 Stack Effect factor 9 Leakage Reduction 2 NMOS9 3 NMOS17 4 NMOS24 2 PMOS8 3 PMOS12 4 PMOS16 00.10.20.30.40.50.60.70.80.91 0 0.5 1 1.5 2 2.5 3 x 10 -9 V M (V) I leak (A) IM1IM1 IM2IM2 90 nm NMOS

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Low Power Design Essentials ©2008 3.33 Gate Tunneling I GD ~ e -Tox e VGD, I GS ~ e -Tox e VGS Independent of the sub-threshold leakage V DD 0V V DD I SUB I GD I GS I Leak Exponential function of supply voltage Modeled in BSIM4 Also in BSIM3v3 (but not always included in foundry models) NMOS gate leakage usually worse than PMOS 90 nm CMOS

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Low Power Design Essentials ©2008 3.34 Other sources of static power dissipation Diode (drain-substrate) reverse bias currents n well n+ p+ p substrate Electron-hole pair generation in depletion region of reverse- biased diodes Diffusion of minority carriers through junction For sub-50nm technologies with highly-doped pn junctions, tunneling through narrow depletion region becomes an issue Strong function of temperature Much smaller than other leakage components in general

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Low Power Design Essentials ©2008 3.35 Other sources of static power dissipation Circuit with dc bias currents: Should be turned off if not used, or standby current should be minimized sense amplifiers, voltage converters and regulators, sensors, mixed-signal components, etc

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Low Power Design Essentials ©2008 3.36 Summary of Power Dissipation Sources – switching activity C L – load capacitance C CS – short-circuit capacitance V swing – voltage swing f – frequency I DC – static current I leak – leakage current

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Low Power Design Essentials ©2008 3.37 The Traditional Design Philosophy Maximum performance is primary goal –Minimum delay at circuit level Architecture implements the required function with target throughput, latency Performance achieved through optimum sizing, logic mapping, architectural transformations. Supplies, thresholds set to achieve maximum performance, subject to reliability constraints

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Low Power Design Essentials ©2008 3.38 CMOS Performance Optimization Sizing: Optimal performance with equal fanout per stage Extendable to general logic cone through logical effort Equal effective fanouts (g i C i+1 /C i ) per stage Example: memory decoder [Ref: I. Sutherland, Morgan-Kaufman98]

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Low Power Design Essentials ©2008 3.39 Model not Appropriate Any Longer Traditional scaling model Maintaining the frequency scaling model While slowing down voltage scaling

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Low Power Design Essentials ©2008 3.40 The New Design Philosophy Maximum performance (in terms of propagation delay) is too power-hungry, and/or not even practically achievable Many (if not most) applications either can tolerate larger latency, or can live with lower than maximum clock-speeds Excess performance (as offered by technology) to be used for energy/power reduction Trading off speed for power

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Low Power Design Essentials ©2008 3.41 1 2 3 4 -0.4 0 0.4 0.8 0 0.2 0.4 0.6 0.8 1 x 10 -4 V TH (V) V DD (V) Power (W) A B For a given activity level, power is reduced while delay is unchanged if both V DD and V TH are lowered such as from A to B. Relationship Between Power and Delay [Ref: T. Sakurai and T. Kuroda, numerous references]

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Low Power Design Essentials ©2008 3.42 The Energy-Delay Space V TH V DD Equal performance curves Energy minimum Equal energy curves

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Low Power Design Essentials ©2008 3.43 Energy-Delay Product as a Metric delay energy energy-delay 90 nm technology V TH approx 0.35V Energy-delay exhibits minimum at approximately 2 V TH (typical unless leakage dominates) 0.60.70.80.911.11.2 0 0.5 1 1.5 2 2.5 3 3.5 V DD

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Low Power Design Essentials ©2008 3.44 In energy-constrained world, design is trade-off process Minimize energy for a given performance requirement Maximize performance for given energy budget Delay Unoptimized design D max D min Energy E min E max Exploring the Energy-Delay Space Pareto-optimal designs [Ref: D. Markovic, JSSC04]

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Low Power Design Essentials ©2008 3.45 Summary Power and energy are now primary design constraints Active power still dominating for most applications –Supply voltage, activity and capacitance the key parameters Leakage becomes major factor in sub-100nm technology nodes –Mostly impacted by supply and threshold voltages Design has become energy-delay trade-off exercise!

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Low Power Design Essentials ©2008 3.46 References D. Markovic, V. Stojanovic, B. Nikolic, M.A. Horowitz, R.W. Brodersen, Methods for True Energy-Performance Optimization, IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp. 1282-1293, Aug. 2004. J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2 nd ed, Prentice Hall 2003. Takayasu Sakurai, Perspectives on power-aware electronics, Digest of Technical Papers ISSCC, pp. 26-29, Febr. 03. I. Sutherland, B. Sproull, and D. Harris, Logical Effort, Morgan Kaufmann, 1999. H. Veendrick, Short-Circuit Dissipation of Static CMOS Circuitry and its Impact on the Design of Buffer Circuits, IEEE Journal of Solid-State Circuits, Vol. SC-19, no. 4, pp.468–473, 1984.

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