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Chapter 3 Logic Gates

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Inverter

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Inverter Truth Table

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**Inverter Timing Diagram**

Figure Inverter operation with a pulse input. Figure The inverter complements an input variable.

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**Inverter Timing Diagram**

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AND gate

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**Figure 3--9 All possible logic levels for a 2-input AND gate.**

AND Gate Operation Figure All possible logic levels for a 2-input AND gate.

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AND Gate Truth Table Figure Boolean expressions for AND gates with two, three, and four inputs.

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AND Gate Truth Table

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**AND Gate Timing Diagram**

Figure Example of pulsed AND gate operation with a timing diagram showing input and output relationships.

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**AND Gate Timing Diagram**

All must be high for the output to be high

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**AND Gate Application Example**

Figure An AND gate performing an enable/inhibit function for a frequency counter.

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OR Gate

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**Figure 3--18 All possible logic levels for a 2-input OR gate**

OR Gate Operation Figure All possible logic levels for a 2-input OR gate

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OR Gate Truth Table Figure Boolean expressions for OR gates with two, three, and four inputs.

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OR Gate Timing Diagram Figure Example of pulsed OR gate operation with a timing diagram showing input and output time relationships.

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OR Gate Timing Diagram All must be low for the output to be low

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**OR Gate Application Example**

Figure A simplified intrusion detection system using an OR gate.

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NAND Gate

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**Figure 3--26 Operation of a 2-input NAND gate.**

NAND Gate Operation Figure Operation of a 2-input NAND gate.

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NAND Gate Truth Table

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**NAND Gate Timing Diagram**

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**Figure 3--29 Standard symbols representing the two equivalent operations of a NAND gate.**

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NOR Gate

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**Figure 3--34 Operation of a 2-input NOR gate.**

NOR Gate Operation Figure Operation of a 2-input NOR gate.

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NOR Gate Truth Table

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**NOR Gate Timing Diagram**

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**Figure 3--37 Standard symbols representing the two equivalent operations of a NOR gate.**

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XOR Gate

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**Figure 3--42 All possible logic levels for an exclusive-OR gate**

XOR Gate Operation Figure All possible logic levels for an exclusive-OR gate

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XOR Gate Truth Table

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**XOR Gate Application Example**

Figure An XOR gate used to add two bits.

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XNOR Gate

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**Figure 3--45 All possible logic levels for an exclusive-NOR gate.**

XNOR Gate Operation Figure All possible logic levels for an exclusive-NOR gate.

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XNOR Gate Truth Table

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**Fixed-Function Logic : IC Gates**

CMOS (Complementary Metal-Oxide Semiconductor) TTL (Transistor-Transistor Logic) CMOS – lower power dissipation

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Figure Typical dual in-line (DIP) and small-outline (SOIC) packages showing pin numbers and basic dimensions.

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**Figure 3--50 Pin configuration diagrams for some common fixed-function IC gate configurations.**

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Figure Logic symbols for hex inverter (04 suffix) and quad 2-input NAND (00 suffix). The symbol applies to the same device in any CMOS or TTL series.

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**Performance Characteristics and Parameters**

Propagation delay Time DC Supply Voltage (VCC) Power Dissipation Input and Output Logic Levels Speed-Power product Fan-Out and Loading

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**Figure 3--52 Propagation Delay**

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**Higher fan-out = gate can be connected to more gate inputs.**

Figure The LS TTL NAND gate output fans out to a maximum of 20 LS TTL gate inputs.

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**Figure 3--57 The partial data sheet for a 74LS00.**

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**Figure 3--59 The effect of an open input on a NAND gate.**

Troubleshooting Figure The effect of an open input on a NAND gate.

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**Figure 3--60 Troubleshooting a NAND gate for an open input with a logic pulser and probe.**

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**Figure 3--65 An example of a basic programmable OR array.**

Programmable Logic Programmable Arrays Figure An example of a basic programmable OR array.

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**Figure 3--66 An example of a basic programmable AND array.**

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**Figure 3--67 Block diagram of a PROM (programmable read-only memory).**

4 Types of SPLDs Figure Block diagram of a PROM (programmable read-only memory).

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**Figure 3--68 Block diagram of a PLA (programmable logic array).**

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**Figure 3--69 Block diagram of a PAL (programmable array logic).**

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**Figure 3--70 Block diagram of a GAL (generic array logic).**

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**Figure 3--71 Logic Gate Summary**

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