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1 Chapter 3 Logic Gates

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2 Inverter

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3 Inverter Truth Table

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4 Inverter Timing Diagram Figure 3--2 Inverter operation with a pulse input. Figure 3--6 The inverter complements an input variable.

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5 Inverter Timing Diagram

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6 AND gate

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7 Figure 3--9 All possible logic levels for a 2-input AND gate. AND Gate Operation

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8 AND Gate Truth Table Figure Boolean expressions for AND gates with two, three, and four inputs.

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9 AND Gate Truth Table

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10 AND Gate Timing Diagram Figure Example of pulsed AND gate operation with a timing diagram showing input and output relationships.

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11 AND Gate Timing Diagram All must be high for the output to be high

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12 Figure An AND gate performing an enable/inhibit function for a frequency counter. AND Gate Application Example

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13 OR Gate

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14 Figure All possible logic levels for a 2-input OR gate OR Gate Operation

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15 OR Gate Truth Table Figure Boolean expressions for OR gates with two, three, and four inputs.

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16 OR Gate Timing Diagram Figure Example of pulsed OR gate operation with a timing diagram showing input and output time relationships.

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17 OR Gate Timing Diagram All must be low for the output to be low

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18 OR Gate Application Example Figure A simplified intrusion detection system using an OR gate.

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19 NAND Gate

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20 Figure Operation of a 2-input NAND gate. NAND Gate Operation

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21 NAND Gate Truth Table

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22 NAND Gate Timing Diagram

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23 Figure Standard symbols representing the two equivalent operations of a NAND gate.

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24 NOR Gate

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25 NOR Gate Operation Figure Operation of a 2-input NOR gate.

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26 NOR Gate Truth Table

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27 NOR Gate Timing Diagram

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28 Figure Standard symbols representing the two equivalent operations of a NOR gate.

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29 XOR Gate

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30 XOR Gate Operation Figure All possible logic levels for an exclusive-OR gate

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31 XOR Gate Truth Table

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32 XOR Gate Application Example Figure An XOR gate used to add two bits.

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33 XNOR Gate

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34 XNOR Gate Operation Figure All possible logic levels for an exclusive-NOR gate.

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35 XNOR Gate Truth Table

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36 Fixed-Function Logic : IC Gates CMOS (Complementary Metal-Oxide Semiconductor) TTL (Transistor-Transistor Logic) CMOS – lower power dissipation

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37 Figure Typical dual in-line (DIP) and small-outline (SOIC) packages showing pin numbers and basic dimensions.

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38 Figure Pin configuration diagrams for some common fixed-function IC gate configurations.

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39 Figure Logic symbols for hex inverter (04 suffix) and quad 2-input NAND (00 suffix). The symbol applies to the same device in any CMOS or TTL series.

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40 Performance Characteristics and Parameters Propagation delay Time DC Supply Voltage (VCC) Power Dissipation Input and Output Logic Levels Speed-Power product Fan-Out and Loading

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41 Figure Propagation Delay

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42 Figure The LS TTL NAND gate output fans out to a maximum of 20 LS TTL gate inputs. Higher fan-out = gate can be connected to more gate inputs.

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43 Figure The partial data sheet for a 74LS00.

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44 Figure The effect of an open input on a NAND gate. Troubleshooting

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45 Figure Troubleshooting a NAND gate for an open input with a logic pulser and probe.

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46 Programmable Logic Programmable Arrays Figure An example of a basic programmable OR array.

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47 Figure An example of a basic programmable AND array.

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48 Figure Block diagram of a PROM (programmable read-only memory). 4 Types of SPLDs

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49 Figure Block diagram of a PLA (programmable logic array).

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50 Figure Block diagram of a PAL (programmable array logic).

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51 Figure Block diagram of a GAL (generic array logic).

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52 Figure Logic Gate Summary

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