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**Designing Static CMOS Logic Circuits**

EE141 Designing Static CMOS Logic Circuits

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EE141 Static CMOS Circuits At every point in time (except during the switching transients) each gate output is connected to either V DD or ss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).

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**Static Complementary CMOS**

EE141 Static Complementary CMOS VDD In1 PMOS only In2 PUN … InN F(In1,In2,…InN) In1 In2 PDN … NMOS only InN One and only one of the networks (PUN or PDN) is conducting in steady state PUN and PDN are logically dual logic networks

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**NMOS Transistors in Series/Parallel Connection**

EE141 NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high

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**PMOS Transistors in Series/Parallel Connection**

EE141 PMOS Transistors in Series/Parallel Connection

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**Threshold Drops VDD VDD PUN VDD 0 VDD 0 VDD - VTn VGS CL CL PDN**

EE141 Threshold Drops VDD VDD PUN S D VDD D S 0 VDD 0 VDD - VTn VGS CL CL PDN VDD 0 VDD |VTp| Why PMOS in PUN and NMOS in PDN … threshold drop NMOS transistors produce strong zeros; PMOS transistors generate strong ones VGS CL CL D S VDD S D

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**Complementary CMOS Logic Style**

EE141 Complementary CMOS Logic Style

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EE141 Example Gate: NAND

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EE141 Example Gate: NOR

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**Complex CMOS Gate B C A D OUT = D + A • (B + C) A D B C EE141**

Shown synthesis of pull up from pull down structure D B C

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**Constructing a Complex Gate**

EE141 Constructing a Complex Gate Logic Dual need not be Series/Parallel Dual In general, many logical dual exist, need to choose one with best characteristics Use Karnaugh-Map to find good duals Goal: find 0-cover and 1-cover with best parasitic or layout properties Maximize connections to power/ground Place critical transistors closest to output node A A D (b) Deriving the pull-up network B hierarchically by identifying sub-nets V B (c) complete gate DD V C DD C A SN2 SN3 D SN4 SN1 C (a) pull-down network F F D F C B A D B

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**Example: Carry Gate F = (ab+bc+ac)’ Carry ‘c’ is critical**

AB’ 1 A’B’ A’B F = (ab+bc+ac)’ Carry ‘c’ is critical Factor c out: F=(ab+c(a+b))’ 0-cover is n-pd 1-cover is p-pu

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**Example: Carry Gate (2) Pull Down is easy**

Order by maximizing connections to ground and critical transistors For pull up – Might guess series dual– would guess wrong

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**Example: Carry Gate (3) Series/Parallel Dual 3-series transistors**

2 connections to Vdd 7 floating capacitors

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**Example: Carry Gate (4) Pull Up from 1 cover of Kmap**

Get a’b’+a’c’+b’c’ Factor c’ out 3 connections to Vdd 2 series transistors Co-Euler path layout Moral: Use Kmap!

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**Cell Design Standard Cells Datapath Cells General purpose logic**

EE141 Cell Design Standard Cells General purpose logic Can be synthesized Same height, varying width Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width

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**Standard Cell Layout Methodology – 1980s**

EE141 Standard Cell Layout Methodology – 1980s Routing channel VDD signals Contacts and wells not shown. What does this implement?? GND

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**Standard Cell Layout Methodology – 1990s**

EE141 Standard Cell Layout Methodology – 1990s Mirrored Cell No Routing channels VDD VDD M2 Contacts and wells not shown. What does this implement?? M3 GND Mirrored Cell GND

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**Standard Cells Cell height 12 metal tracks**

EE141 Standard Cells N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” V DD Out In 2 Rails ~10 GND Cell boundary

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**Standard Cells With minimal diffusion routing With silicided diffusion**

EE141 Standard Cells With minimal diffusion routing V DD With silicided diffusion V DD Out In Out In GND GND

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EE141 Standard Cells 2-input NAND gate V DD A B Out GND

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**Stick Diagrams Contains no dimensions**

EE141 Stick Diagrams Contains no dimensions Represents relative positions of transistors V DD V DD Inverter NAND2 Out Out In A B GND GND

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**Stick Diagrams Logic Graph j VDD X i GND A B C PUN PDN A j C B**

EE141 Stick Diagrams Logic Graph j VDD X i GND A B C PUN PDN A j C B X = C • (A + B) C i Systematic approach to derive order of input signal wires so gate can be laid out to minimize area Note PUN and PDN are duals (parallel <-> series) Vertices are nodes (signals) of circuit, VDD, X, GND and edges are transitions A B A B C

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**Two Versions of C • (A + B)**

EE141 Two Versions of C • (A + B) A C B A B C VDD VDD X X Line of diffusion layout – abutting source-drain connections Note crossover eliminated by A B C ordering GND GND

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**Consistent Euler Path X C i VDD X B A j A B C GND EE141**

A path through all nodes in the graph such that each edge is visited once and only once. The sequence of signals on the path is the signal ordering for the inputs. PUN and PDN Euler paths are (must be) consistent (same sequence) If you can define a Euler path then you can generate a layout with no diffusion breaks A B C C A B B C A no PDN B A C A C B -> no PDN C B A A B C GND

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**OAI22 Logic Graph X PUN A C D C B D VDD X X = (A+B)•(C+D) C D B A A B**

EE141 OAI22 Logic Graph X PUN A C D C B D VDD X X = (A+B)•(C+D) C D B A A B PDN A GND B C D

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EE141 Example: x = ab+cd

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**Properties of Complementary CMOS Gates Snapshot**

EE141 Properties of Complementary CMOS Gates Snapshot High noise margins : V and V are at V and GND , respectively. OH OL DD No static power consumption : There never exists a direct path between V and DD V ( GND ) in steady-state mode . SS Comparable rise and fall times: (under appropriate sizing conditions)

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**CMOS Properties Full rail-to-rail swing; high noise margins**

EE141 CMOS Properties Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratioless Always a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady-state input current No direct path steady state between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistors

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**Switch Delay Model Req A A B Rp A Rn CL Cint CL B Rn A Rp Cint A Rp A**

EE141 Switch Delay Model Req A A B Rp A Rn CL Cint CL B Rn A Rp Cint A Rp A Rp A Rn CL Note capacitance on the internal node – due to the source grain of the two fets in series and the overlap gate capacitances of the two fets in series NOR2 INV NAND2

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**Input Pattern Effects on Delay**

EE141 Input Pattern Effects on Delay Delay is dependent on the pattern of inputs Low to high transition both inputs go low delay is 0.69 Rp/2 CL one input goes low delay is 0.69 Rp CL High to low transition both inputs go high delay is Rn CL A Rp B Rp CL Rn B A Rn Cint

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**Delay Dependence on Input Patterns**

EE141 Delay Dependence on Input Patterns Input Data Pattern Delay (psec) A=B=01 67 A=1, B=01 64 A= 01, B=1 61 A=B=10 45 A=1, B=10 80 A= 10, B=1 81 A=B=10 A=1 0, B=1 Voltage [V] A=1, B=10 Gate sizing should result in approximately equal worst case rise and fall times. Reason for difference in the last two delays is due to internal node capacitance of the pulldown stack. When A transitions, the pullup only has to charge CL; when A=1 and B transitions pullup have to charge up both CL and Cint. For high to low transitions (first three cases) delay depends on state of internal node. Worst case happens when internal node is charged up to VDD – VTn. Conclusions: Estimates of delay can be fairly complex – have to consider internal node capacitances and the data patterns. time [ps] NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF

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**Transistor Sizing CL B Rn A Rp Cint B Rp A Rn CL Cint 4 2 2 1 EE141**

Assumes Rp = Rn 1

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**Multi-Fingered Transistors**

EE141 Multi-Fingered Transistors One finger Two fingers (folded) Less diffusion capacitance

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**Transistor Sizing a Complex CMOS Gate**

EE141 Transistor Sizing a Complex CMOS Gate A B 8 6 4 3 C 8 6 D 4 6 OUT = D + A • (B + C) For class lecture. Red sizing assuming Rp = Rn Follow short path first; note PMOS for C and B 4 rather than 3 – average in pull-up chain of three – (4+4+2)/3 = 3 Also note structure of pull-up and pull-down to minimize diffusion cap at output (e.g., single PMOS drain connected to output) Green for symmetric response and for performance (where Rn = 3 Rp) Sizing rules of thumb PMOS = 3 * NMOS 1 in series = 1 2 in series = 2 3 in series = 3 etc. A 2 D 1 B 2 C 2

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**Fan-In Considerations**

EE141 Fan-In Considerations A B C D CL A Distributed RC model (Elmore delay) tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case. C3 B C2 C While output capacitance makes full swing transition (from VDD to 0), internal nodes only transition from VDD-VTn to GND C1, C2, C3 on the order of 0.85 fF for W/L of 0.5/0.25 NMOS and 0.375/0.25 PMOS CL of 3.2 fF with no output load (all diffusion capacitance – intrinsic capacitance of the gate itself). To give a 80.3 psec tpHL (simulated as 86 psec) C1 D

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**tp as a Function of Fan-In**

EE141 tp as a Function of Fan-In tpHL quadratic linear tp Gates with a fan-in greater than 4 should be avoided. tp (psec) tpLH Fixed fan-out (NMOS 0.5 micrcon, PMOS 1.5 micron) tpLH increases linearly due to the linearly increasing value of the diffusion capacitance tpHL increase quadratically due to the simultaneous incrase in pull-down resistance and internal capacitance fan-in

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**tp as a Function of Fan-Out**

EE141 tp as a Function of Fan-Out All gates have the same drive current. tpNOR2 tpNAND2 tpINV tp (psec) Slope is a function of “driving strength” slope is a function of the driving strength eff. fan-out

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**tp as a Function of Fan-In and Fan-Out**

EE141 tp as a Function of Fan-In and Fan-Out Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to CL tp = a1FI + a2FI2 + a3FO a1 term is for parallel chain, a2 term is for serial chain, a3 is fan-out

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**Practical Optimization**

The previous arguments regarding tp raise the question – why build nor at all? Criticality is not a path– but a transition so it is usually only on rising or falling (but not both) NOR forms have bad pull-up but good pull down NAND forms have bad pull-down but good pull up Determine the critical transition(s) and design for them– using Elmore or Simulation on the appropriate edge only! Logical Effort presupposes uniform rise and fall times, so good in general, but can be beat Static Timing Analyzers nearly always get this wrong!

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**Fast Complex Gates: Design Technique 1**

EE141 Fast Complex Gates: Design Technique 1 Transistor sizing as long as fan-out capacitance dominates Progressive sizing CL Distributed RC line M1 > M2 > M3 > … > MN (the fet closest to the output is the smallest) InN MN M1 have to carry the discharge current from M2, M3, … MN and CL so make it the largest MN only has to discharge the current from MN (no internal capacitances) C3 In3 M3 C2 In2 M2 Can reduce delay by more than 20%; decreasing gains as technology shrinks C1 In1 M1

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**Fast Complex Gates: Design Technique 2**

EE141 Fast Complex Gates: Design Technique 2 Transistor ordering critical path critical path 01 CL CL charged charged 1 In1 In3 M3 M3 1 C2 1 C2 In2 In2 M2 discharged M2 charged For lecture. Critical input is latest arriving signal Place latest arriving signal (critical path) closest to the output 1 C1 C1 In3 discharged In1 charged M1 M1 01 delay determined by time to discharge CL, C1 and C2 delay determined by time to discharge CL

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**Fast Complex Gates: Design Technique 3**

EE141 Fast Complex Gates: Design Technique 3 Alternative logic structures F = ABCDEFGH Reduced fan-in -> deeper logic depth Reduction in fan-in offsets, by far, the extra delay incurred by the NOR gate (second configuration). Only simulation will tell which of the last two configurations is faster, lower power

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**Fast Complex Gates: Design Technique 4**

EE141 Fast Complex Gates: Design Technique 4 Isolating fan-in from fan-out using buffer insertion CL CL Reduce CL on large fan-in gates, especially for large CL, and size the inverters progressively to handle the CL more effectively

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**Fast Complex Gates: Design Technique 5**

EE141 Fast Complex Gates: Design Technique 5 Reducing the voltage swing linear reduction in delay also reduces power consumption But the following gate may be much slower! Large fan-in/fan-out requires use of “sense amplifiers” to restore the signal (memory) tpHL = 0.69 (3/4 (CL VDD)/ IDSATn ) = 0.69 (3/4 (CL Vswing)/ IDSATn )

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**Sizing Logic Paths for Speed**

Frequently, input capacitance of a logic path is constrained Logic also has to drive some capacitance Example: ALU load in an Intel’s microprocessor is 0.5pF How do we size the ALU datapath to achieve maximum speed? We have already solved this for the inverter chain – can we generalize it for any type of logic?

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**Buffer Example In Out CL 1 2 N (in units of tinv)**

EE141 Buffer Example In Out CL 1 2 N (in units of tinv) For given N: Ci+1/Ci = Ci/Ci-1 To find N: Ci+1/Ci ~ 4 How to generalize this to any logic path?

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EE141 Logical Effort p – intrinsic delay (3kRunitCunitg) - gate parameter f(W) g – logical effort (kRunitCunit) – gate parameter f(W) f – effective fanout Normalize everything to an inverter: ginv =1, pinv = 1 Divide everything by tinv (everything is measured in unit delays tinv) Assume g = 1.

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**Delay in a Logic Gate Gate delay: d = h + p effort delay**

EE141 Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = Cout/Cin Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size

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EE141 Logical Effort Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current Logical effort increases with the gate complexity

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EE141 Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g = 1 g = 4/3 g = 5/3

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**Logical Effort of Gates**

EE141 Logical Effort of Gates t pNAND g = p = d = pINV t Normalized delay (d) g = p = d = F(Fan-in) 1 2 3 4 5 6 7 Fan-out (h)

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**Logical Effort of Gates**

EE141 Logical Effort of Gates t pNAND g = 4/3 p = 2 d = (4/3)h+2 pINV t Normalized delay (d) g = 1 p = 1 d = h+1 F(Fan-in) 1 2 3 4 5 6 7 Fan-out (h)

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EE141 Add Branching Effort Branching effort:

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**Multistage Networks Stage effort: hi = gifi**

Path electrical effort: F = Cout/Cin Path logical effort: G = g1g2…gN Branching effort: B = b1b2…bN Path effort: H = GFB Path delay D = Sdi = Spi + Shi

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**Optimum Effort per Stage**

EE141 Optimum Effort per Stage When each stage bears the same effort: Stage efforts: g1f1 = g2f2 = … = gNfN Effective fanout of each stage: Minimum path delay

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**Optimal Number of Stages**

EE141 Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing Substitute ‘best stage effort’

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EE141 Logical Effort From Sutherland, Sproull

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**Method of Logical Effort**

EE141 Method of Logical Effort Compute the path effort: F = GBH Find the best number of stages N ~ log4F Compute the stage effort f = F1/N Sketch the path with this number of stages Work either from either end, find sizes: Cin = Cout*g/f Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

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**Example: Optimize Path**

EE141 Example: Optimize Path g = 1 f = a g = 5/3 f = b/a g = 5/3 f = c/b g = 1 f = 5/c Effective fanout, F = G = H = h = a = b =

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**Example: Optimize Path**

EE141 Example: Optimize Path g = 1 f = a g = 5/3 f = b/a g = 5/3 f = c/b g = 1 f = 5/c Effective fanout, F = 5 G = 25/9 H = 125/9 = 13.9 h = 1.93 a = 1.93 b = ha/g2 = 2.23 c = hb/g3 = 5g4/f = 2.59

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**Example: Optimize Path**

EE141 Example: Optimize Path g4 = 1 g1 = 1 g2 = 5/3 g3 = 5/3 Effective fanout, H = 5 G = 25/9 F = 125/9 = 13.9 f = 1.93 a = 1.93 b = fa/g2 = 2.23 c = fb/g3 = 5g4/f = 2.59

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EE141 Example – 8-input AND

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EE141 Summary Sutherland, Sproull Harris

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Homework 5 Using the Carry cell design from earlier homework, optimally size the carry propagate chain for a 16-bit adder to minimize worst case delay where Cin is driven by a 1u/0.6u inverter and Cout drives a fanout of 4 such loads. (use logic effort, show your work!) For the problems below, use parameters from class for 0.5um and use 2x voltages as applicable. Chap 5: problems: 4, 7, 8, 15 Chap 6, problems: 2, 4, 5, 7 Design the parity tree: c = a xor b xor c xor d in Complementary Pass Transistor Logic, insert inverters to restore the output swing – Given input drive from an inverter stage, and an inverter every 2 stages of logic, and inverter output restore, estimate the propagation time for devices using the AMI 0.5um model. New (digital) AMI model (for minimum length only!): n-channel: VT=0.77, l=0.03, Vsat=1.56V, k=32mA/V2 p-channel: VT=-0.95, l=0.03 Vsat=2.8V, k=-16mA/V2

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