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ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 1 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Licensed.

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1 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 1 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Licensed Electrical & Mechanical Engineer BMayer@ChabotCollege.edu Engineering 43 Sequential (FlipFlop) Logic

2 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 2 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis But First… WhiteBoard Work  For the Truth Table Shown at right Construct the Karnaugh Map Write The Minimized Function Q(A,B,C,D) Draw the Logic Circuit  Notice “1’s” in Rows 1, 5, 9, 13, 14, 15 –Need only put “1’s” in these locations; other cells Assumed to be Zero Row ABCDQ 0 00000 1 00011 2 00100 3 00110 4 01000 5 01011 6 01100 7 01110 8 10000 9 10011 10 10100 11 10110 12 11000 13 11011 14 11101 15 11111

3 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 3 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Blank Map (NonStretching)  Can TYPE in these Maps AB\CD00011110 00 0112 11 10 AB\CD00011110 00 A’B’C’D’A’B’C’DA’B’CDA’B’CD’ 01 A’BC’D’A’BC’DA’BCDA’BCD’ 11 ABC’D’ABC’DABCDABCD’ 10 AB’C’D’AB’C’DAB’CDAB’CD’

4 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 4 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Stretchable Blank Map (by Hand)

5 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 5 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis New Subj: NAND Gate Synthesis  Implement Arbitrary SOP Logic Fcn in NAND Gates Only Check that Fcn can be placed in K-Map by putting Expression in CANONICAL form Minimize the K-Map if possible Use Inverter Made from NAND gate if needed (if only Positive InPuts Available) Invert entire Fcn Twice such that DeMorgan to converts the SOP to Nest-of-NANDS Check by Inverting a second time

6 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 6 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis De Morgan’s Laws

7 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 7 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis NAND Gate Synthesis PreReq  Assume that ALL Inputs are available ONLY in the HI, or 1, form.  If 0 needed use NAND-Based inverter: AB

8 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 8 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis More… WhiteBoard Work  Implement This New EXAMPLE Function using ONLY NAND Gates  An Example of NAND-Gate Synthesis NANDS are easier to construct than ANDs, ORs, NORs –NANDs are the preferred gate for logic circuits

9 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 9 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis NAND Synthesis

10 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 10 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis NAND Synthesis

11 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 11 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis “Memory Filled” Logic  The Invert/AND/OR Combinatorial Logic Circuits depended ONLY on the Current Inputs; previous states did Not affect the Current State Combinatorial Logic is MemoryLESS  In SEQUENTIAL Logic the Circuit Output CAN Depend on the Previous condition of the Circuit Sequential Logic is MemoryFUL

12 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 12 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Sequential Circuit  A sequential circuit consists of a feedback path, and employs some memory elements  [Sequential circuit] = [Combinational logic] + [Memory Elements] Combinational logic Memory elements Combinational outputs Memory outputs External inputs

13 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 13 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Synchronous vs Asynchronous  Almost all Logic “Chips” Include a Clock  The Clock helps to “Synchronize” the Operation of the Circuits.  The “Clock” is simply a very regular Hi/Lo Pulse train   Logic Forms are divided into two groups: SYNCHRONUS → Depend on Clock Asynchronous → NO Clock-Dependency

14 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 14 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Asynchronous S-R FlipFlop  Cross-coupled NOR gates Similar to inverter pair, with capability to force Q = 0 ([S,R]=[0,1]) or Q = 1 ([S,R]=[1,0]) R S Q Q' R S Q 0 1 0 1 R S Q 1 0 1 0 R S Q n-1 0 0 R S Q Q' ?? 1 1 Reset Set UnDet Memory [R,S] =[0,0] → [R’,S’] =[1,1] NOR → any HI = LO, else Hi

15 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 15 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis NAND based SR FlipFlop  Cross-Coupled NAND gates Similar to inverter pair, with capability to force Q = 0 ([S,R]=[0,1]) or Q = 1 ([S,R]=[1,0]) R' S' QQ Q' S' R' NOR notes  Any HI input → LO output Any HI → LO  All LO inputs → HI output All LO → HI (else HI)  Any LO input → HI output Any LO → HI  All HI inputs → LO output All HI → LO (else LO) NAND notes [R,S] =[0,0] → [R’,S’] =[1,1] NAND → any LO = HI, else Lo

16 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 16 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis State Behavior of SR FlipFlop  Transition (NOT Truth) Table  Sequential (output depends on history when inputs R=0, S=0) but asynchronous R S Q Q' SRQ n-1 Q n 0000 0011 0100 0110 1001 1011 110X 111X hold reset set not allowed characteristic equation Q n = S∙ R’ + R’∙Q n-1 SETREset NOR: Any “1” forces a “0”

17 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 17 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis NOR SR FlipFlop Timing Reset Hold Set Reset Race R S Q Q’ 100 R S Q Q'  “Races” Produce UnPredictable OutPuts  Any HI input → LO output Any HI → LO  All LO inputs → HI output All LO → HI Q n = R’∙(S + Q n-1 )

18 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 18 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Clocked SR FlipFlop  Control times when R and S inputs matter Otherwise, the slightest glitch on R or S while enable is low could cause change in value stored Ensure R & S stable before utilized (to avoid transient R=1, S=1) NOR: Any “1” forces a “0”

19 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 19 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Clocked SR FlipFlops  NOR-NOR Implementation  Truth Table For NOR: any-Hi→LO; ALL-LO→Hi R’S’En’RSQnQn 00011NotAllowed 01010Reset to 0 10001Set to 1 11x00Q n−1 xx100 x → Don’t Care NOR → any HI = LO, else Hi

20 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 20 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Clocked SR FlipFlops  AND-NOR Implementation AND: any-0 → 0 NOR: any-1 → 0  Truth Table RSCQnQn 00xQ n−1 011Set to 1 101Reset to 0 111NotAllowed xx0Q n−1 x → Don’t Care Circuit Symbol

21 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 21 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis SR FlipFlop Clock-Overide  Sometimes Need to Set or Reset the FlipFlop withOUT Regard to the Clock  Note the position of Pr & Cl on the 3 rd -Stage ORs (any Hi→Hi) Ensures Pr & Cl OverRide R, S, & C OR: Any “1” forces a “1” (toggle armed)

22 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 22 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Edge Triggered D FlipFlop  sensitive to inputs only near edge of clock signal (not while steady ) Q D Clk=1 R S 0 D’ 0 D Q’ holds D' when clock goes low holds D when clock goes low NOR: Any “1” forces a “0” (toggle armed)

23 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 23 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Edge-Triggered FlipFlop Flavors Edge-Triggered FlipFlop Flavors  POSITIVE edge-triggered flip-flops Inputs sampled on RISING edge; outputs change just after the RISING edge  NEGATIVE edge-triggered flip-flops Inputs sampled on falling edge; outputs change just after the falling edge positive edge-triggered FF negative edge-triggered FF D CLK Qpos Qpos' Qneg Qneg' 100  D=0  Reset  D=1  Set

24 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 24 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Edge Triggered D FlipFlop  4-NAND, 1-NOT implementation  Truth Table for All Postive-Going Edge D-FF’s NAND: –any LO → Hi –All HI → LO CLKDQnQn 0xQ n−1 1x ↑00 ↑11 NAND → any LO = HI, else Lo

25 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 25 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Edge Triggered JK FlipFlop  A “Toggling” Flip Flop Under a certain Control-Set: Q → Q’ –Notice that Q does NOT go HI-for-sure or LO-for-sure, and it does NOT remain STEADY  A NAND Nest: Circuit Symbol

26 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 26 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis JK FlipFlop Toggle TruthTable  The Simplified Ckt  Note that the outputs feed back to the enabling NAND gates. This is what gives the toggling action when J=K=1  ReCall NAND Any LO → Hi ALL Hi → LO CJKQnQn Notes 0xxQ n−1 No Chg 1xxQ n−1 No Chg ↓00Q n−1 No Chg ↓010Reset to 0 ↓101Set to 1 ↓11Q’ n−1 TOGGLE

27 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 27 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Cascading FF → Shift Register  Serial-in/Parallel-out Shift register New value goes into first stage While previous value of 1 st stg goes into 2 nd stg The Q N can be SAMPLED any time CLK IN Q0Q1 DQDQOUT

28 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 28 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example: Eliminate Inconsistency DQ DQ Q0 Clock Q1 Async Input Clocked Synchronous System INput is asynchronous and fans out to D0 and D1 one FF catches the signal, one does not inconsistent state may be reached! In Q0 Q1 CLK DQ DQ Q0 Clock Q1 Async Input DQ Synchronizer Want to Send SAME Input Value to TWO Places Using Q0 & Q1

29 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 29 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis FlipFlops Summarized  Development of D-FF Level-sensitive used in custom integrated circuits –can be made with 4 pairs of gates –Usually follows multiphase non-overlapping clock discipline Edge-triggered used in programmable logic devices –Good choice for data storage register

30 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 30 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis FlipFlops Summarized  Historically the J-K FlipFlop was popular but now never used Similar to R-S but with 1-1 being used to toggle output (complement state) Same Operation Can always be implemented using D FlipFlops  Preset and Clear inputs are highly desirable on FlipFlops Used at start-up or to reset system to a known state

31 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 31 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis FlipFlops Summarized  Reset (set state to 0)  R Synchronous: D new = R' D old –Transition only when next clock edge arrives Asynchronous: doesn't wait for clock –quick but dangerous by “Race” Possibilities  Preset or Set (set state to 1)  S Synchronous: D new = D old + S –Transition only when next clock edge arrives Asynchronous: doesn't wait for clock –quick but dangerous by “Race” Possibilities

32 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 32 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis WhiteBoard Work  Use Gates and a D-FF to Implement the JK-FF operation CJKQnQn Notes 0xxQ n−1 No Chg 1xxQ n−1 No Chg ↓00Q n−1 No Chg ↓010Reset to 0 ↓101Set to 1 ↓11Q’ n−1 TOGGLE

33 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 33 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis All Done for Today IEEE 91-1984 Gates

34 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 34 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Licensed Electrical & Mechanical Engineer BMayer@ChabotCollege.edu Engineering 43 Appendix Logic Syn

35 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 35 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

36 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 36 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

37 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 37 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis NAND Gate Synthesis PreReq  Assume that ALL Inputs are available ONLY in the HI, or 1, form.  If 0 needed use NAND-Based inverter: AB

38 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 38 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis NAND Gate Synthesis  With the expression in SOP form 1.After any needed inversions (using NAND inverter); In the first logic level there are as many logic gates as terms in the SOP expression 2.Each gate corresponds to a SINGLE Term, and has, as inputs, the variables in that term 3.The outputs of the First Logic-Level are ALL inputs to a SINGLE (multi-input if needed) NAND gate

39 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 39 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis F is an ARBITRARY Example as Previously Set by the logic Designer

40 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 40 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

41 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 41 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

42 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 42 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

43 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 43 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

44 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 44 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

45 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 45 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

46 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 46 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

47 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 47 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

48 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 48 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

49 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 49 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

50 BMayer@ChabotCollege.edu ENGR-43_Lec-05c_Thevenin_AC_Power.pptx 50 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

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