1. 1 Lecture 20 Sequential Circuits: Latches

2. 2 Overview °Circuits require memory to store intermediate data °Sequential circuits use a periodic signal to determine when to store values. A clock signal can determine storage times Clock signals are periodic °Single bit storage element is a flip flop °A basic type of flip flop is a latch °Latches are made from logic gates NAND, NOR, AND, OR, Inverter

3. 3 Combination Vs Sequential °Combinational Circuits Combinational circuits have only input and output. Output depends on input. Example: AND,OR,NAND,NOR,XOR etc °Sequential Circuits Sequential circuits have input, present state, next state and output. Next state depends upon present state and input. Output depends upon present state and input Example: Flip-Flops etc °A Sequential Circuit can be defined as circuit having sequential logic. Sequential logic is a type of a logic circuit whose output depends not only on current inputs but also on previous inputs.

4. 4 What exactly is memory? °A memory should have at least three properties 1.It should be able to hold a value. 2.You should be able to read the value that was saved 3.You should be able to change the value that’s saved A one-bit bi-stable memory 1.It should be able to hold a single bit, 0 or 1 (two possible stable states) 2.You should be able to read the bit that was saved 3.You should be able to change the value. Since there’s only a single bit, there are only two choices: –Set the bit to 1 –Reset, or clear, the bit to 0

5. 5 Bi-stable Binary Storage Elements °Simple Circuits with Feedback Primitive memory elements created from cascaded gates Simplest gate component: inverter Basis for commercial static RAM designs Cross-coupled NOR gates and NAND gates also possible Static Memory Cell Z LD A 0 1 s v "0" "1" AZ

6. 6 The story so far... °Logical operations which respond to combinations of inputs to produce an output. Call these combinational logic circuits. °For example, can add two numbers. But: No way of adding two numbers, then adding a third (a sequential operation); No way of remembering or storing information after inputs have been removed. °To handle this, we need sequential logic capable of storing intermediate (and final) results.

7. 7 Basic structure °The basic structure of a synchronous sequential circuit is shown here. °Synchronous – One input is a clock and on the clock the next state becomes the present state of the system. °Sequential – The circuit transitions between states in a regular manner.

8. 8 Definitions °Inputs – All the outside logic signal inputs to the circuit. Typically, the clock is not consider part of the signal inputs of the circuit. °Outputs – The logic signal outputs. °Present State – the logic value of all the state variables of the system. These are stored in the state memory. °Next State – Given the present state and the current values on the inputs, the next state represents the next logic state the circuit will transition to on the next clock.

9. 9 Sequential Circuits Combinational circuit Flip Flops Outputs Inputs Next state Present state Timing signal (clock) Clock a periodic external event (input) Clock a periodic external event (input) synchronizes when current state changes happen keeps system well-behaved makes it easier to design and build large systems synchronizes when current state changes happen keeps system well-behaved makes it easier to design and build large systems

10. 10 Cross-coupled Inverters State 1 State 2 °A stable value can be stored at inverter outputs

11. 11 SR Latch °The SR latch below has two inputs S and R, which will let us control the outputs Q and Q’ feed back °Here Q and Q’ feed back into the circuit. They’re not only outputs, they’re also inputs! current °To figure out how Q and Q’ change, we have to look at not only the inputs S and R, but also the current values of Q and Q’: Q next = (R + Q’ current )‘ Q’ next = (S + Q current )‘ °Let’s see how different input values for S and R affect this thing Q: 1-bit state variable

12. 12 Storing a value: SR = 00 °What if S = 0 and R = 0? °The equations on the right reduce to: Q next = (0 + Q’ current )’ = Q current Q’ next = (0 + Q current )’ = Q’ current °So when SR = 00, then Q next = Q current. Whatever value Q has, it keeps °This is exactly what we need to store values in the latch. Q next = (R + Q’ current )’ Q’ next = (S + Q current )’

13. 13 Setting the latch: SR = 10 °What if S = 1 and R = 0? °Since S = 1, Q’ next is 0, regardless of Q current : Q’ next = (1 + Q current )’ = 0 °Then, this new value of Q’ goes into the top NOR gate, along with R = 0. Q next = (0 + 0)’ = 1 So when SR = 10, then Q’ next = 0 and Q next = 1 °This is how you set the latch to 1. The S input stands for “set” °Notice that it can take up to two steps (two gate delays) from the time S becomes 1 to the time Q next becomes 1 °But once Q next becomes 1, the outputs will stop changing. This is a stable state Q next = (R + Q’ current )’ Q’ next = (S + Q current )’

14. 14 Resetting the latch: SR = 01 °What if S = 0 and R = 1? °Since R = 1, Q next is 0, regardless of Q current : Q next = (1 + Q’ current )’ = 0 °Then, this new value of Q goes into the bottom NOR gate, where S = 0 Q’ next = (0 + 0)’ = 1 °So when SR = 01, then Q next = 0 and Q’ next = 1 °This is how you reset, or clear, the latch to 0. The R input stands for “reset” °Again, it can take two gate delays before a change in R propagates to the output Q’ next Q next = (R + Q’ current )’ Q’ next = (S + Q current )’

15. 15 SR latches are memories! °This little table shows that our latch provides everything we need in a memory: we can set it, reset it, and remember the current value. °The output Q represents the data stored in the latch, which is called as the state of the latch. °We can expand the table above into a state table, which explicitly shows that the next values of Q and Q’ depend on their current values, as well as on the inputs S and R.

16. 16 SR latches are sequential! °Notice that for inputs SR = 00, the next value of Q could be either 0 or 1, depending on the current value of Q °So the same inputs can yield different outputs, depending on whether the latch was previously set or reset °This is very different from the combinational circuits that we’ve seen so far, where the same inputs always yield the same outputs.

17. 17 What about SR = 11? °Both Q next and Q’ next will become 0 °This contradicts the assumption that Q and Q’ are always complements °Another problem is what happens if we take S = 0 and R = 0 together. Q next = (0 + 0)’ = 1 Q’ next = (0 + 0)’ = 1 °But these new values go back into the NOR gates, and in the next step we get: Q next = (0 + 1)’ = 0 Q’ next = (0 + 1)’ = 0 °The circuit enters an infinite loop, where Q and Q’ cycle between 0 and 1 forever °This is actually the worst case, but the conclusion is don’t ever set SR=11! Q next = (R + Q’ current )’ Q’ next = (S + Q current )’ 0 0 1 1 0 0 0 0

18. 18 S-R Latch with NORs 1 1 0 0 1 0 S R Q Q ’ 0 1 1 0 Set 1 0 Stable 0 1 Reset 0 0 Undefined R (reset) Q Q S (set) °S-R latch made from cross-coupled NORs °If Q = 1, set state °If Q = 0, reset state °Usually S=0 and R=0 °S=1 and R=1 generates unpredictable results

19. 19 SR Latch Symbols

20. 20 S’R’ latch Q next = (S’. Q’ current )‘ Q’ next = (R’. Q current )’ S’S’R’R’Q curr Q’ curr (S’.Q’ curr )’(R’.Q curr )’Q next 11xx’x’xx’x’ No change 10xx’x’(1. 1)’1 0 (reset) 01xx’x’1(1. 1)’1 (set) 00Avoid

21. 21 Characteristic Table °In order to remember previous inputs, sequential circuits must have some sort of storage element. This storage element is called “flip-flop”. °Flip-flop depends on previous inputs to the circuit. °The basic memory unit is called an SR flip-flop. °We can describe flip-flops using characteristic table. SR Flip-Flop operation (BUILT WITH NOR GATES) Characteristic tableExcitation table SRActionQ(t)Q(t+1)SRAction 00Keep state000X No change 01Q = 00110reset 10Q = 11001set 11 Unstable combinati on 11X0 race condition

22. 22 °1°1 °0°0 Review: Steering Gates °The flow of logic can be controlled with a logic gate. The NAND as a steering gate inverts the input. 1 1 Control 1 0 Signal

23. 23 °1°1 °0°0 Steering Gates °A control input ‘0’ inhibits the signal. 0 1 Control 10 Signal 1

24. 24 °1°1 °0°0 Steering Gates 1 Control 10 Signal °1°1 °0°0 1 1 1 0 Output Enabled (inverted)

25. 25 °1°1 °0°0 Steering Gates 1 Control 1 0 Signal °1°1 °0°0 0 1 1 0 1 1 Output Disabled

26. 26 An SR latch with a control input °Here is an SR latch with a control input C °Notice the hierarchical design! The dotted blue box is the S’R’ latch from the previous slide The additional NAND gates are simply used to generate the correct inputs for the S’R’ latch °The control input acts just like an enable

27. 27 S-R Latch with NANDs S R Q Q’Q’ 0 0 1 1 0 1 S R Q Q ’ 0 1 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed °Latch made from cross-coupled NANDs °Sometimes called S’-R’ latch °Usually S=1 and R=1 °S=0 and R=0 generates unpredictable results

28. 28 S-R Latches

29. 29 S-R Latch with control input °Occasionally, desirable to avoid latch changes °C = 0 disables all latch state changes °Control signal enables data change when C = 1 °Right side of circuit same as ordinary S-R latch.

30. 30 Latch operation enabled by C C Input sampling enabled by gates NOR S-R Latch with Control Input R’R’ S’S’ Q’Q’ Q C’C’ Outputs change when C is low: RESET and SET Otherwise: HOLD Outputs change when C is low: RESET and SET Otherwise: HOLD Latch is level-sensitive, in regards to C Only stores data if C’ = 0

31. 31 Problems with SR Latch °The problem with the SR Latch is that it requires two inputs to store one value. °A latch is needed where one input is applied to store one value. °A control input is also required to place the device in a hold state. °Moreover there is a race condition (undefined)

32. 32 D Latch Q Q’Q’ C D S R X Y X Y C Q Q ’ 0 0 1 Q 0 Q 0 ’ Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q 0 Q 0 ’ Store 0 1 1 1 1 0 X 0 Q 0 Q 0 ’ D C Q Q ’ °Q 0 indicates the previous state (the previously stored value)

33. 33 D Latch Q Q’Q’ C D S R X Y 0 1 1 1 1 0 X 0 Q 0 Q 0 ’ D C Q Q ’ °Input value D is passed to output Q when C is high °Input value D is ignored when C is low

34. 34 D Latch E x Latches on following edge of clock E D Q C x z z °Z only changes when E is high °If E is high, Z will follow X

35. 35 D Latch E x Latches on following edge of clock E D Q C x z z °The D latch stores data indefinitely, regardless of input D values, if C = 0 °Forms basic storage element in computers

36. 36 Symbols for Latches °SR latch is based on NOR gates °S’R’ latch based on NAND gates °D latch can be based on either.

37. 37 Summary °Latches are based on combinational gates (e.g. NAND, NOR) °Latches store data even after data input has been removed °S-R latches operate like cross-coupled inverters with control inputs (S = set, R = reset) °With additional gates, an S-R latch can be converted to a D latch (D stands for data) °D latch is simple to understand conceptually When C = 1, data input D stored in latch and output as Q When C = 0, data input D ignored and previous latch value output at Q