1. Reading Assignment: Rabaey: Chapter 7
ELEC 516 VLSI System Design and Design Automation Spring Lecture 5: Flip-Flop/Latch Design
Reading Assignment:
Rabaey: Chapter 7
Note: some of the figures in this slide set are adapted from the slide set
of “ Digital Integrated Circuits” by Rabaey et. al., Copyright 2002

2. Motivations: Why do we need sequential circuits?
Need memory
Pipeline the system so that new operations start before the old ones complete.
Add registers to keep operations separate.
Convert parallel operations to a sequence of serial operations (faster operations per cycle/ smaller).
Need to process a sequence of inputs and want to reuse the same hardware (Finite State Machine)

3. Sequential Logic Memory Element:F s
LOGIC t
p,comb f In
Out
Memory Element:
Stores a value as controlled by clock.
May have load signal, etc
2 storage mechanisms
positive feedback
charge-based

4. Memory Elements - Latches and flip-flops
A generic memory element has an internal memory and some circuitry to control access to the internal memory. which is controlled by the clock input.
Memory element differ in many key respect:
exactly what form of clock signal causes the input data value to be read;
how the behavior of data around the read signal from clock affects the stored value;
when the stored value is presented to the output;
whether there is a combinational path from the input to the output.
2 types of memory: latches and edge-triggered flip flop
latches - transparent while the internal memory is being set from the data input
edge-triggered flip-flops (or register) - not transparent, reading the input value and changing the flip-flop’s output are two separate events.

5. Simple Circuit with Feedback
One inverter with feedback
Self-oscillation, 2 gate delays for one period
Odd-number of inverters with feedback
self-oscillation of 2x gate delays of one path
Two inverters with feedback
Memory element (or states)
Basis for commercial static RAM designs
Read-only, but has no write function
Memory with read/write capability
Selectively break the feedback path by transmission gates to load new value into the cell
A can be written to Z when LD = 1
Write SW On & Feedback SW Off
Z holds the value when LD = 0
Write SW Off & Feedback SW On
“0?"
"1"
"0"
"1" Z LD
LD’ A

6. Latch versus Register Latch stores data when clock is low D Q D Q Clk
stores data when clock rises D Q D Q
Clk
Clk
Clk
Clk D D Q Q

7. Let’s build a latch Latches are multiplexers controlled by a clock:
When CLK is high data will pass through otherwise the data is saved or kept unchanged feedback from output to input
Can be realized using transmission gates

8. Dynamic latch Stores charge on inverter gate capacitance:
Uses complementary transmission gate to ensure that storage node is always strongly driven.
Latch is transparent when transmission gate is closed.
Storage capacitance comes primarily from inverter gate capacitance.
Setup and hold times determined by transmission gate—must ensure that value stored on transmission gate is solid.

9. Dynamic latch- Stored charge leakage
Stored charge leaks away due to reverse-bias leakage current.
Stored value is good for about 1 ms.
Value must be rewritten to be valid.
If not loaded every cycle, must ensure that latch is loaded often enough to keep data valid.

10. Non-dynamic latches Must use feedback to restore value.
Some latches are static on one phase (pseudo-static)—load on one phase, activate feedback on other phase.
Example - Recirculating latch: Static on one phase:

11. Latch-Based Design N latch is transparent when f = 0
P latch is transparent when f = 1 f N P
Logic
Latch
Latch
Logic

12. Positive Feedback: Bi-Stability
The circuit presents only three operation points
When the gain of the inverter in the transient region is larger than 1, A and B are the only stable operation points & C is a metastable operation point.

13. Meta-Stability Gain should be larger than 1 in the transition region
C is an instable operating point. Every deviation (even small) causes the operation to run away (because of high gain).
A and B are very stable operation points, the loop gain is much smaller than unity, eve a large deviation will not cause deviation from these operation points.

14. Flip states in Bistable Circuit
Two different approaches:
Cutting the feedback loop
Open the loop and write data
Multiplexer based
Q = Clk’.Q + Clk.In
Overpowering the feedback loop
Applying a trigger signal at the input of the flip-flop to overpower the stored value to a new value
Careful sizing of the transistors in the feedback loop and the input is necessary

15. Writing into a Static Latch
Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states D
CLK
Forcing the state
(can implement as NMOS-only)
Converting into a MUX

16. Other styles Small and lower clock load but sizing problems
Very good style
(Skew considerations)
Fast and energy efficient
Presents the lowest
clock load

17. Mux-Based Latch
Positive level latch. When the D path is ON, the feedback is cut-off
No sizing issues for correct operation.
The number of transistors that the clock drives is an issue (clock has an activity factor of 1: CLK Load of four transistors.

18. Mux-Based Latch
NMOS only
Non-overlapping clocks

19. DFF Implementation (falling edge triggered)
Master/Slave latch arrangement Ds D Q D Q D Q G Q’ G Q’ Cs C D Q
Master D latch
Slave D latch C Q’

20. DFF Internal OperationC
Master sampling
Master sampling Ds
Xfer to Slave Cs
Xfer to Slave Q

21. Flip-Flop: Timing Definitions
Setup time: time before clock during which data input must be stable.
Hold time: time after clock event for which data input must remain stable.
Clock-to-Q delay = TPFF

22. Clk-Q Delay

23. The setup time race
Setup represents the race for new data to propagate around the feedback loop before clock closed the input gate.
If data arrives too close to clock edge, it will not set up the feedback loop before clock closed the input TG

24. The hold time race
Hold time represents the race for clock to close the input gate before next cycle’s data disturbs the stored value
If data changes too soon after the clock edge, clock might not had time to switch off the input gate and new data will corrupt feedback loop

25. Setup Time

26. Maximum Clock Frequency
Also:
tcdreg + tcdlogic > thold
tcd: contamination delay = minimum delay
tclk-Q + tp,comb + tsetup = T
Modern high performance systems are characterized by low logic depth
The register’s delay becomes very important as the registers because it
accounts for both the setup and propagation delay.
DEC Alpha up has a max logic depth of 12 gates, &15% of the delay
corresponds to the register overhead.

27. Reduced Clock Load Master-Slave Register
Eliminate the feedback transmission gate.
Possible problem: reverse conduction

28. Clock Overlap Problem Potential problems:X
CLK
CLK Q A D B
(a) Schematic diagram
CLK
CLK
Potential problems:
Race condition: data at the output change at the rising edge of the clock
Node A can be driven by both D and B when clock overlap
CLK
CLK
(b) Overlapping clock pairs
Variations in the routing wires
Used to route CLK & CLK’
Variations on the load
Inverter’s delay

29. 2 phase Non-overlapping clock DFF
Two-phase non-overlapping clocks

30. 6 Transistor CMOS SR-Flip Flop

31. Dynamic Latches and registers
Disadvantage of static FF - complexity, larger size
The requirement that the memory should hold state for extended periods of time can be relaxed in computational structure
Dynamic - use the charge stored in capacitance to eliminate the use of inverter pair to latch data: Pseudo-static latch (Charge-Based Storage) A D
Clk
Clk’ B Q
Clk=1: The input data is sampled on storage node A, during this time the slave is on hold mode, node B at high impedance.
On the falling edge of the clock, T2 turns ON and the value sampled on A propagates to the output.
Setup time is the delay of the transmission gate
Hold time is zero since the TG is turned off on the clock edge.
Tc2q= delay of two inverters and a transmission gate.

32. Making a Dynamic Latch Pseudo-Static
Fully dynamic circuit presents a number of drawbacks:
Capacitive coupling can inject significant noise to the internal storage node.
Leakage current: Most modern processors require that the clock can be slowed down or completely halted to conserve power in low activity periods
Most of these problems can be addressed by adding a weak feedback inverter  Pseudo-Static Latch
Slight cost in delay and silicon area.
Improves noise immunity significantly
Dynamic latches should be made Pseudo-Static, keep for very special cases of highly controlled environment (full-custom, high performance data path design)

33. Impact of non-overlapping clocksD
Clk
Clk’ B Q T1 T2
clk
During the (0,0) overlap, PMOS of T1 and PMOS of T2 are ON, creating a direct path from D to Q.
The same problem appears during the (1,1) overlap.
clk
(0,0)
Overlap
(1,1)
Overlap
Overlapping Clocks Can Cause
Race Conditions
Undefined Signals

34. Flip-flop insensitive to clock overlapDD DD M 2 M 6 f M 4 f M 8 X In D C C f M 3 L 1 f M 7 L 2 M 1 M 5 f-
section f -
section C 2
MOS LATCH

35. C2MOS avoids Race ConditionsIn 1 M 3 2 6 7 5 V DD 4 8
(a) (1-1) overlap
(b) (0-0) overlap X
During the (0,0) overlap, new data sampled on the falling edge of the clock
will not appear at D output.
Same remark applied during the (1,1) overlap.

36. Operation of the C2MOS latch
When f = 1, M3 and M4 are on, the 1st section is in the evaluation mode and the second section is in a hold mode (high impedance). M7 and M8 are off, decoupling the output from the input. The input D retains its previous value stored on the output capacitance.
When f = 0, the first section is in hold mode and the second section is in evaluation mode, the value stored in CL1 propagates to the output node.
A C2MOS register with (f - f ) clocking is insensitive to overlap, as long as rise and fall times of the clock edges are sufficiently small.

37. Dual Edge registers
Dual Edge registers are very interesting as they permit to run the Clock 2 times slower  lower power on the clock node. D f N1 X N2 Q Y

38. Pipelined Logic using C2MOSF
Out f V DD f V DD
NORA CMOS G C C C 1 2 3
What are the constraints on F and G?
No-race rule: A C2MOS-based pipelined circuit is race-free as long as the logic function F (static logic) between the latches are non-inverting

39. Example f V DD V DD f 1 f
Number of a static inversions should be even

40. Doubled C2MOS Latches-True single-phase clock registerf V DD
Out V V DD DD In In f f
Out
Doubled n-C2 MOS latch
(transparent when CLK= 1)
Doubled p-C2 MOS latch
(transparent when CLK= 0)
+ Requires a single clock to build a positive & negative clock
- Can suffer from charge sharing & noise pbs when clk low.

41. TSPC - True Single Phase Clock Logicf V DD In
Static
Logic
PUN
PDN f V DD
Out
Including logic into
Inserting logic between
the latch
latches

42. Example of Including Logic in TSPC
CLK V DD Q In 1 2
Embedding logic into the latch reduces the delay overhead of the latch.
This approach of embedding logic into the latch was extensively used in many high performance microprocessors including EV4 DEC Alpha.
AND latch

43. Master-Slave Flip-flopsDD D f V DD D f V DD D f V DD D Y X D
(a) Positive edge-triggered D flip-flop
(b) Negative edge-triggered
D flip flop
(c) Positive edge-triggered D flip-flop
using split-output latches

44. Pulse-Triggered Latches An Alternative Approach
Ways to design an edge-triggered sequential cell:
IDEA: construct a short pulse around the rising (or falling)
edge of the clock. This would be the NEW clock input.
Hold time is equal to the length of the pulse.
Master-Slave Latches
Pulse-Triggered Latch L1 L2 L
Data
Data D Q D Q D Q
Clk
Clk
Clk
Clk
Clk
+ Reduced clock load, small number of transistors required.
+ Glitch circuitry can be shared by multiple register.
- increase in verification complexity: Need to make sure the glitch
Is properly generated!!!!!

45. Pulsed Latches
Glitch corresponds
to the delay of the
AND + 2 Inv

46. Pulsed Latches Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :
When the clock is low: M3 and M6 are off and P1 is ON. Node X is precharged to VDD, and the output is decoupled from X (Memory).
CLKD’ is a delayed-inverted version of CLK. On the rising edge of the clock, M3 and M6 turn ON while M1 and M4 stay ON for a short period, and hence the latch is transparent and D is sampled. Once CLKD’ goes low node X is decoupled from D.

47. Hybrid Latch-FF Timing
Advantage: Setup time can be negative: Transparency window
Is longer than the delay from input to the output.
D injected after
the clock.

48. Pipelining
REG
LOG a b
Out f
REG a b f
LOG
REG
Out f
REG f
REG f

49. Latch-Based Pipeline

50. NORA (NO Race) CMOS Modules
f block
Logic
Latch
f =0
f =1
Precharge
Hold
Evaluate

51. Non-Bistable Sequential Circuits─ Schmitt Trigger
VTC with hysteresis
Restores signal slopes

52. Noise Suppression using Schmitt Trigger

53. CMOS Schmitt Trigger
Moves switching threshold
of the first inverter

54. Schmitt Trigger Simulated VTC
2.5
2.5
2.0
2.0 V
1.5 M 1
1.5
(V)
(V) X x
1.0 V
1.0 V M 2 V k
= 1 k
= 3 k
= 2
0.5
0.5 k
= 4
0.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5 V
(V) V
(V) in in
Voltage-transfer characteristics with hysteresis.
The effect of varying the ratio of the
PMOS device M
. The width is k
* m. m 4

55. CMOS Schmitt Trigger (2)

56. Multivibrator Circuits

57. Transition-Triggered Monostable

58. Monostable Trigger (RC-based)

59. Astable Multivibrators (Oscillators)1 2
N-1
Ring Oscillator
simulated response of 5-stage oscillator

60. Voltage Controller Oscillator (VCO)

61. Differential Delay Element and VCO
ctrl o 2 1 in
delay cell v 1 2 3 4 in 2
two stage VCO
0.5
0.0
1.0
1.5
2.0
2.5
3.0 2 V 1 3 4
time (ns)
3.5
simulated waveforms of 2-stage VCO