ba A B B1 FADC B2 SD_FP FLEX_I/O ROC VME64x A: [ HELICITY, HELICITY_FLIP ] (NIM or ECL) Port 1 Port 2 a: [ HELICITY, HELICITY_FLIP ] (LVDS) B: [ HELICITY_TRIGGER, DATA_TRIGGER ] (ECL) b: [ HELICITY_TRIGGER, DATA_TRIGGER ] (LVDS) Moller DAQ with the FADC250 NIM / ECL LVDS CR SR CL SL CR: CALORIMETER RIGHT [1-4] SR: SCINTILLATOR RIGHT [1-4] CL: CALORIMETER LEFT [1-4] SL: SCINTILLATOR LEFT [1-4] Figure M1

Overview Scintillator and calorimeter signals from the left and right halves of a Moller polarimeter are input into the FADC. Using the flexibility and speed of the FPGA, various logical quantities based on digital sums and hit patterns of the inputs is computed (see detailed description later). Some of these quantities (5) are scaled, while others (3) are used to trigger the capture of the input pulses that produced them. The comparison of the scaler values for the beam in its two helicity states is the object of the study. Figure M2 shows the free-running accelerator signals HELICITY and HELICITY_FLIP. These are input as control signals into the FADC front panel (after level conversion by the SD_FP module). The assertion of HELICITY_FLIP indicates that the helicity state is in transition, so scalers and triggers are disabled during this time. When the user issues GO to start a data run, enabling of scalers and triggers (ENABLE_MOLLER) will not begin until the trailing edge of the next HELICITY_FLIP pulse. Similarly, when GO is negated, acquisition will continue until the leading edge of the next HELICITY_FLIP pulse. In this way, data will always be acquired for an integral number of valid helicity periods (ENABLE_MOLLER). At the end of each ENABLE_MOLLER period, scaler data (ten 16-bit words) is transferred from the Moller FPGA to the Control FPGA over the 16-bit control bus. It is stored in an internal FIFO as six 32-bit words (1 header + 5 scalers). The header identifies the helicity state (bit 31) and the helicity interval number (bits 30-0). When the transfer is complete, the scalers are cleared. They are enabled to count again when ENABLE_MOLLER is asserted. At the end of each ENABLE_MOLLER period, the pulse HELICITY_TRIGGER is output from the FADC front panel. This is used to interrupt the Read Out Controller (ROC) so that the scaler data can be read out. This is done by routing the signal to port 1 of the FLEX I/O module (after level conversion by the SD_FP). For each internally generated trigger, the helicity state and trigger pattern are stored as a single word in the MOLLER FIFO. As the ADC data is being collected, the trigger word is transferred to the Control FPGA over the control bus, and appears as a type 10 (user defined) data word in the event. Data from internally generated triggers is stored on the FADC until a programmed number (block, 255 maximum) of events is acquired. When this happens, a pulse (DATA_TRIGGER) is issued from the FADC front panel. This signal is routed to port 2 of the FLEX I/O module (after level translation by the SD_FP module). The FLEX I/O interrupts the ROC so that the block of events may be read out. When the read out is complete, the ROC acknowledges the transfer and re-enables DATA_TRIGGER generation.

HELICITY HELICITY_FLIP GO ENABLE_MOLLER TRANSFER SCALERS CLEAR SCALERS HELICITY TRIGGER ( START RUN )( END RUN ) ACQUIRE DATA AQUIRE DATA Figure M2

HALL A Moller Polarimeter Requirement SCIN TILL ATOR CAL ORI MET ER LEFT SCIN TILL ATOR CAL ORI MET ER RIGHT FADC ON BOARD SCALER (COUNTER) to be read out by a separate trigger (helicity and gate bits) at the helicity cycle of 30 to 2kHz. CL and CR CL and SL CR and SR CL and CR and SL and SR CL and CR and (SL and SR delayed > 100 ns) TRIGGER condition (or): CL.AND.CR prescaled from 1 to at least 1000 CL prescaled from 1 to at least 1000 CR prescaled from 1 to at least 1000 CL = Σ I=1,4 ∑ j=1,2 P J I > threshold CR = Σ I=1,4 ∑ j=1,2 P J I > threshold SL = (Σ J=1,2 S1 J > threshold) or (ΣJ=1,2 S2 J > threshold) or (ΣJ=1,2 S3 J > threshold) or (ΣJ=1,2 S4 J > threshold) SR = (Σ J=1,2 S5 J > threshold) or (ΣJ=1,2 S6 J > threshold) or (ΣJ=1,2 S7 J > threshold) or (ΣJ=1,2 S8 J > threshold) When TRIGGER condition is met, send data that cause TRIGGER

Xilinx LX25 ADC 16 9 ADC 8 1 Xilinx LX25 Xilinx FX20 24 FIFO ALTERA STRATIX2 Control Bus Front Panel Lvds Trig, Sync BACK Plane Trig, Sync VME BUS FADC HARDWARE ARCHITECTURE

Xilinx LX25 ADC L Calorimeter ( ADC ) ADC Xilinx LX25 Xilinx FX20 Cal Sum 16) Scint Hit (4) FIFO ALTERA STRATIX2 Trig Type, Trig Count, Helicity, Gate Front Panel Helicity Gate VME BUS trigger MOLLER DAQ FIRMWARE ARCHITECTURE TOP LEVEL trigger Trig Ready Capture Data Cal Sum 16) Scint Hit (4) R Calorimeter (ADC 8..5) L Scint (ADC12..9) R Scint (ADC 4..1)

MOLLER DAQ FIRMWARE ARCHITECTURE Xilinx LX25 TRIGGER Cal 1 0 G en1 Cal 4 0 G en4 Scint1 0 G en5 Scint4 0 G en8 No change to Look Back Algorithm 8 0 S en1 0 GS en4 + SUM G  Global > Threshold > HIT Threshold REG + + SL = ∑ j=1,2 S J > Th x SR = ∑ j=1,2 S J > Th x C = Σ I=1,4 P I HISTORY Cal 1-4 Scint 1-4 Trigger Capture Data To FIFO

Trigger to ALtera FPGA Hit Pattern to FIFO enable Trig Ready from ALtera FPGA MOLLER DAQ FIRMWARE ARCHITECTURE Xilinx FX20 1 st LX25 SUM CR 2 nd LX25 SUM CL 1 st LX 25 HIT Px DELAY 2 nd LX 25 HIT Px DELAY 4 4 TRIGGER LOGIC En Clear 32 bits Counter En Clear 32 bits Counter En Clear 32 bits Counter En Clear 32 bits Counter CONTROLBUSCONTROLBUS AUX(0) AUX(1) CNT_CTRL bit from Altera TRIG TYPE (CR*CL) (CL*SL) (CR*SR) (CL*CR*SL*SR) CL CR P Prescalar Trig pattern Trig Type P  Programmable SR SL 4 4 Px DELAY -2X-Pn > Px FixWidth P Threshold Px DELAY -2X-Pn > P Threshold Px FixWidth SL SR Px DELAY (min 100 ns) d(SL*SR) En Clear 32 bits Counter (CL*CR*d(SL*SR) Helicity(aux2), TrigCount CL = ∑ j=1,2 P J CR = ∑ j=1,2 P J En 12 bits Counter Trig Ready Hit Window

CL_Prescale CR_Prescale CLandCR Prescale CL CR CLandCR Trigger MOLLER DAQ FIRMWARE ARCHITECTURE Xilinx FX20 (Hit Window) Clr En Counter = 8 s c c e c e c e

MOLLER DAQ FIRMWARE ARCHITECTURE Altera FPGA Control FRONT PANEL HELICITY TRIG FROM FX20 TRIG READY TO FX20 AUX(0)TO FX20 TRIG TO LX25

MOLLER DAQ FIRMWARE ARCHITECTURE Altera FPGA Control FRONT PANEL HELICITY TRIG FROM FX20 TRIG READY TO FX20 AUX(0)TO FX20 TRIG TO LX25