1. NA62 Trigger Algorithm Trigger and DAQ meeting, 8th September 2011 Cristiano Santoni Mauro Piccini (INFN – Sezione di Perugia) NA62 collaboration meeting, Mainz 6-9 September 2011 Trigger Algorithm

2. Introduction NA62 collaboration meeting, 8th September 2011Trigger Algorithm To re-use the NA48 hodoscope for the 2012 run we need a new read-out, TEL62 will be the core of the new system and already at L0 this could allow: Correction for the impact point position of L0 time produced by CHOD - O(1ns) Slewing correction, given the fixed threshold of the NINO chip - O(100ps) Word type

3. Data Flow NA62 collaboration meeting, 8th September 2011Trigger Algorithm Two different algorithms to be implemented: Slewing correction: we need both leading and trailing edges measured from TDC Impact point: the trailing will only be considered initially to validate the hit and to allow the use of the leading time; today we will focus on this algorithm, so trailings will not be considered here. The TDC data must be properly grouped in order to identify hits coming from the same physics event (grouping is limited by the available information at this level) Since the algorithm combinatory will strongly influence the computation time, a maximum number of tracks per quadrant (3 ?) and a maximum number of tracks per event (5 ?) will be considered If these maxima will be exceeded only the average time of the hits will be computed and a word (“too complex” or “high multiplicity”) could be sent to the L0 processor

4. Sub-bin Creation NA62 collaboration meeting, 8th September 2011Trigger Algorithm t Timestamp n n-1 n+1 T max 2T max hit Already included in an event of the previous bin In each bin, corresponding to a clock period (40 MHz  25 ns), the hits not already included in an event will be grouped considering a T MAX (5 ns ?) time window. If between T MAX and 2T MAX other hits will be present, time differences will be computed and the hits will be “properly” grouped 25 ns

5. from TDC2 Data Reorganization Trigger and DAQ meeting, 8th September 2011Trigger Algorithm from TDC0 from TDC1 from TDC3 from TDC1 from TDC0 from TDC3 from TDC0 from TDC1 from TDC0 from TDC3 from TDC2 from TDC3 Data from Vertical Plane Data from Horizontal Plane In this step data are divided into two groups according to the plane they refer to. In order to get the belonging plane, we have to test the bits 5-8: TDC0 and TDC1 refer to the vertical plane while TDC2 and TDC3 refer to the horizontal one from TDC0 from TDC1 from TDC2 from TDC0 from TDC3 5ns Sub-bin

6. Pairs Generation for Data Correction Trigger and DAQ meeting, 8th September 2011Trigger Algorithm Now we want to correct the measured times from the TDCs taking into account the delay introduced by the scintillators. To do so we have to consider any pairs between an element belonging to the vertical plane and another from the horizontal one (taking care that they correspond to the same quadrant). We don’t have enough information to know where the particle is exactly passed so what we do is to generate any possible pair introducing fake coincidences.

7. Correction Array Addressing Trigger and DAQ meeting, 8th September 2011Trigger Algorithm To correct data, we use an array (LUT), addressed by the words that make up the pair. Two bits coming from the vertical plane word identify the quadrant and then the four LSBs of each hit identify the position of the coincidence. The LUT contains 12-bit words of which the six MSBs are the correction for the vertical plane time and the six LSBs are the correction for the horizontal plane time (both in hundreds of ps) TDC0 – Channel 10 0000 01010 TDC2 – Channel 6 0010 00110 xxxxxx 010110 010010 xxxxxx 00 1010 0110 00 1010 0101 00 1010 0100 00 1010 0111 00 1010 1000 Correction : 2.2ns V. time 1.8ns H. time Q V. ch H. ch

8. Correction Array as Spatial mask Trigger and DAQ meeting, 8th September 2011Trigger Algorithm Since the scintillators have different length, there are some impossible channel combinations (for example channel 16 vertical with channel 1 horizontal). To discard these fake tracks, instead of create a complex condition, we simply insert at the corresponding array row a particular word that “corrects” of 6,4ns only the vertical plane word. Doing so these pairs will be discarded by the minimum- finding logic. Using this technique we can also specify a spatial mask to exclude an instrumented area simply by editing the array configuration file (see S.Balev talk on 13 th July, HAC/MUV WG)

9. Discovering the real tracks Trigger and DAQ meeting, 8th September 2011Trigger Algorithm Now we have to choose the pairs of data generated from a physics event and discard those generated by noise and fake coincidences. After all the data are corrected by the LUT, we select the pair with the minimum temporal difference, deleting every other pair containing at least one of these two hits. We repeat these two steps until at least one of the termination condition, that we are going to see, will be met H. 12 V. 4 H. 15 V. 5 MIN Too much delay => it’s not a track! Real track t

10. Termination Condition Trigger and DAQ meeting, 8th September 2011Trigger Algorithm The operations presented in the previous slide are repeated until one of these conditions is satisfied: 1) There are max_quadr_evn (parameter – 3?) events on the same quadrant 2) There is a total of max_tot_evn (parameter – 5?) events 3) The selected pair has a temporal distance greater than max_delta_t (parameter – 2ns?) t Max_delta_t 1 23

11. Trigger and DAQ meeting, 8th September 2011Trigger Algorithm The complexity of the operations, and then of logic that implements them, slows down the frequency at which the design can work and then the processing rate. To speed up the processing rate we have two non-exclusive ways: 1)To introduce a pipeline architecture 2)To generate more instances of the trigger logic to enable parallel processing Performance Improvement Proc. Block 1 Proc. Block 2 input output Buffer 1 input Trigger Logic Trigger Logic output Proc. Block N Buffer N-1 … 2) 1)

12. Performance Improvement: Pipeline Trigger and DAQ meeting, 8th September 2011Trigger Algorithm Introducing a pipeline architecture, we are able to reduce the processing time from the sum of the processing times of each step of the algorithm to the maximum of them. To apply this type of architecture, the steps of our algorithm must not to have any feedback, so each step works only on data produced from the previous step and produces data only for the next step. Any processed data cannot be reassessed afterwards. from Binning Logic 5ns Bin Generation Buffer Plane-based Sorting Buffer Pairs Generation Buffer Pairs Correction Buffer Iterative Minimum Finding Output

13. Trigger and DAQ meeting, 8th September 2011Trigger Algorithm Another way to improve the processing rate is to generate more than one instance of the trigger logic. The restriction for such architecture is that every instance of logic have to operate on an independent set of data. In our specific case, we can do better than simply “copy and paste” logic, we can create different types of logic based on different inputs. For example we can create a high performance algorithm for sub-bin containing only two words (one track) Performance Improvement: Parallelization # of word? 2-word-optimized trigger logic Generic trigger logic 3-word-optimized trigger logic Output merge

14. Firmware simulation NA62 collaboration meeting, 8th September 2011Trigger Algorithm Once the firmware will be completed it will be debugged first by using the logic simulation to ensure the logic correctness and afterwards using a timing simulation Input data will be produced taking into account event rate and event multiplicity extracted directly from the Geant4 simulation of the beam and the detector Hit position will also be considered according to Geant4 simulation

15. Conclusion NA62 collaboration meeting, 8th September 2011Trigger Algorithm At this moment we have implemented a first simplified version of the algorithm which compute the minimum temporal difference among the possible tracks in a 25ns bin. This first version has been tested using logic simulation and it works fine. For the simulation software tools have been already created to input data to the algorithm. Such tools generate input file from any given distribution of events and noise. Our aims is to have at least the logic simulation of the complete algorithm done and running for the dicember meeting.