ECE2030 Introduction to Computer Engineering Lecture 11: Building Blocks for Combinational Logic (2) Decoders/Encoders, Comparators Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

2 1-to-2-Line DecoderAD1D D0 D1 A

3 N-to-M-Line Decoder (2 N  M) A1A0D3D2D1D D0D0 D1D1 D2D2 D3D3 2-to-4-linedecoder A0A0 A1A1

4 2-to-4-Line Decoder A1A0D3D2D1D How about if no one should be enabled ? A1 A0 D0 D1 D2 D3

5 2-to-4-Line Decoder w/ Enable EnA1A0D3D3 D2D2 D1D1 D0D0 0XX D0D0 D1D1 D2D2 D3D3 2-to-4-linedecoder A0A0 A1A1 En

6 2-to-4-Line Decoder w/ Enable EnA1A0D3D3 D2D2 D1D1 D0D0 0XX A1 A0 D0 D1 D2 D3 En

7 3-to-8-Line Decoder A2A1A0D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D Truth Table

8 3-to-8-Line Decoder A2A1A0D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D Truth Table

9 3-to-8-Line Decoder A2A1A0D7D6D5D4D3D2D1D D0D0 D1D1 D2D2 D3D3 2-to-4-linedecoder A0A0 A1A1 En D0D0 D1D1 D2D2 D3D3 D0D0 D1D1 D2D2 D3D3 2-to-4-linedecoder A0A0 A1A1 D4D4 D5D5 D6D6 D7D7 A0A0 A1A1 A2A2

10 Implementing Logic w/ Decoder D0D0 D1D1 D2D2 D3D3 3-to-8-linedecoder A0A0 A1A1 A2A2 D4D4 D5D5 D6D6 D7D7 X Y Z F1 F2

11 BCD-to-7- Segment Decoder BCD-to-7-Segment Decoder Another kind of decoder a b c d e f g a b c d e f g A B C D

12 BCD-to-7- Segment Decoder BCD-to-7-Segment Decoder Another kind of decoder a b c d e f g a b c d e f g A B C D a b c d e g f

13 BCD-to-7- Segment Decoder BCD-to-7-Segment Decoder Decode “2” and show a b c d e f g a b c d e f g A B C D a b c d e g f

14 BCD-to-7- Segment Decoder BCD-to-7-Segment Decoder Decode “4” and show a b c d e f g a b c d e f g A B C D a b c d e g f

15 BCD-to-7-Seg. Decoder Truth Table ABCDabcdefg >10All other inputs

16 Design Each Output Individually  “a” ABCDa >10All other inputs AB CD

17 Design Each Output Individually  “b” ABCDb >10All other inputs AB CD

18 M-to-N-Line Encoder (M  2 N ) D0D0 D1D1 D2D2 D3D3 2-to-4-lineDecoder A0A0 A1A1 En D0D0 D1D1 D2D2 D3D3 4-to-2-lineEncoder A0A0 A1A1 Ac

19 4-to-2 Encoder D3D2D1D0A1A Since Dx=1 only in one column at a time A0 = D1 + D3 A1 = D2 + D X0X1 01 0XXX 11 XXXX 10 1XXX D3 D2 D1 D0 For A X0X0 01 1XXX 11 XXXX 10 1XXX D3 D2 D1 D0 For A1

20 8-to-3 Encoder D7D6D5D4D3D2D1D0A2A1A Since Dx=1 only in one column at a time A0 = D1 + D3 + D5 + D7 A1 = D2 + D3 + D6 + D7 A2 = D4 + D5 + D6 + D7

21 Example 1 of an Encoder Only point to one single reading at a time.

22 Example 2 of an Encoder D0D0 D1D1 D2D2 D3D3 8-to-3-lineEncoder A0A0 A1A1 A2A2 D4D4 D5D5 D6D6 D7D7 Amy Brian Cathy Dave Ellen Frank Gina Hugh Ac Active or not ? ? ? 1

23 8-to-3 Priority Encoder D7D6D5D4D3D2D1D0A2A1A0Active X XX XXX XXXX XXXXX XXXXXX1101 1XXXXXXX1111

24 4-to-2 Priority Encoder D3D2D1D0A1A0Active X011 01XX101 1XXX D3 D2 D1 D0 For A1 Or using simplification property

25 4-to-2 Priority Encoder D3D2D1D0A1A0Active X011 01XX101 1XXX D3 D2 D1 D0 For A0 Or using simplification property

26 4-to-2 Priority Encoder D3D2D1D0A1A0Active X011 01XX101 1XXX D3 D2 D1 D0 For Active

27 4-to-2 Priority Encoder Schematic D3 D2 D1 D0 A1 A0 Active

28 8-to-3 Priority Encoder (A2) D7D6D5D4D3D2D1D0A2A1A0Active X XX XXX XXXX XXXXX XXXXXX1101 1XXXXXXX1111

29 8-to-3 Priority Encoder (A1) D7D6D5D4D3D2D1D0A2A1A0Active X XX XXX XXXX XXXXX XXXXXX1101 1XXXXXXX1111

30 8-to-3 Priority Encoder (A0) D7D6D5D4D3D2D1D0A2A1A0Active X XX XXX XXXX XXXXX XXXXXX1101 1XXXXXXX1111

31 8-to-3 Priority Encoder (All) D7D6D5D4D3D2D1D0A2A1A0Active X XX XXX XXXX XXXXX XXXXXX1101 1XXXXXXX1111

32 1-bit Magnitude Comparator ABA?B 00A=B 01A<B 10A>B 11A=B AB A > B A = B A < B Single bit comparison

33 2-bit Magnitude Comparator (unsigned) AB A > B A = B A < B Two-bit comparison 2 2 A1A0B1B0A1A0B1B0

34 2-bit Magnitude Comparator (unsigned) AB A > B A = B A < B Two-bit comparison 2 2 A1A0B1B0A1A0B1B0

35 3-bit Magnitude Comparator (unsigned) Three-bit comparison A2A1A0B2B1B0A2A1A0B2B1B0 AB A > B A = B A < B 3 3

36 4-bit Magnitude Comparator (unsigned) Four-bit comparison A3A2A1A0B3B2B1B0A3A2A1A0B3B2B1B0 AB A > B A = B A < B 4 4

37 4-bit Magnitude Comparator B3A3A2A1A0B2B1B0 X3 X2 X1 X0 A>BA<B A=B

38 Cascading Comparator AB A > B A = B A < B 4 4 AGTBin AGTBout AEQBout ALTBout Inputs from Prior stage Lower order bits (Lower order bits) AEQBin ALTBin Extra Comb. Logic Outputs to Next stage Higher order bits (Higher order bits) AGTBout = (A>B) + (A=B) · AGTBin AEQBout = (A=B) · AEQBin ALTBout = (A<B) + (A=B) · ALTBin

39 16-bit Cascading Comparator AB AGTBin AEQBin ALTBin 4 4 AGTBout AEQBout ALTBout A[3:0] B[3:0] AB AGTBin AEQBin ALTBin 4 4 AGTBout AEQBout ALTBout A[7:4] B[7:4] AB AGTBin AEQBin ALTBin 4 4 AGTBout AEQBout ALTBout A[11:8] B[11:8] AB AGTBin AEQBin ALTBin 4 4 AGTBout AEQBout ALTBout A[15:12] B[15:12] A>B A<B A=B B[15:0] A[15:0]