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Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Logic and Computer Design Fundamentals Lecture 14 – Combinational Functional Blocks

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Chapter 4 2 Overview Functions and functional blocks Enabling Decoding Encoding Selecting

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Chapter 4 3 Functions and Functional Blocks Higher-level functions Common in real designs Simplify design process Add hierarchy and replication Implemented within a functional block. In the past, many functional blocks were implemented as SSI, MSI, and LSI chips. Today, they are often simply parts within a VLSI circuits.

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Chapter 4 4 Enabling Function Enabling permits an input signal to pass through to an output Disabling blocks an input signal from passing through to an output, replacing it with a fixed value The value on the output when it is disable can be Hi-Z (as for three-state buffers and transmission gates), 0, or 1 When disabled, 0 output When disabled, 1 output See Example 4-2 in text

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Chapter 4 5 Decoding - the Conversion of n-bit input to m-bit output Given n m 2 n Circuits that perform decoding are called decoders Called n-to-m line decoders, where m 2 n, and Generate 2 n (or fewer) minterms for the n input variables Decoding

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Chapter 4 6 1-to-2-Line Decoder 2-to-4-Line Decoder Note that the 2-4-line made up of 2 1-to-2- line decoders and 4 AND gates. Decoder Examples

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Chapter 4 7 Decoder Expansion - Example Result

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Chapter 4 8 In general, attach m-enabling circuits to the outputs See truth table below for function Note use of X’s to denote both 0 and 1 Combination containing two X’s represent four binary combinations Alternatively, can be viewed as distributing value of signal EN to 1 of 4 outputs In this case, called a demultiplexer Decoder with Enable

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Chapter 4 9 Encoding Encoding - the opposite of decoding Conversion of m-bit input to n-bit output Circuits that perform encoding are called encoders An encoder has 2 n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corres-ponding to the position in which the 1 appears.

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Chapter 4 10 Encoder Example A decimal-to-BCD encoder Inputs: 10 bits corresponding to decimal digits 0 through 9, (D 0, …, D 9 ) Outputs: 4 bits with BCD codes Function: If input bit D i is a 1, then the output (A 3, A 2, A 1, A 0 ) is the BCD code for i, The truth table could be formed, but alternatively, the equations for each of the four outputs can be obtained directly.

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Chapter 4 11 Encoder Example (continued) Input D i is a term in equation A j if bit A j is 1 in the binary value for i. Equations: A 3 = D 8 + D 9 A 2 = D 4 + D 5 + D 6 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 0 = D 1 + D 3 + D 5 + D 7 + D 9 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

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Chapter 4 12 Priority Encoder What if multiple inputs are true? Encoder just designed does not work. Instead, use a priority encoder. Encodes either Most significant input position Or least significant input position

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Chapter 4 13 Priority Encoder Example Priority encoder with 5 inputs (D 4, D 3, D 2, D 1, D 0 ) - highest priority to most significant 1 present - Code outputs A2, A1, A0 and V where V indicates at least one 1 present. Xs in input part of table represent 0 or 1; thus table entries correspond to product terms instead of minterms. The column on the left shows that all 32 minterms are present in the product terms in the table No. of Min- terms/Row Inputs Outputs D4D3D2D1D0A2A1A0V 100000XXX0 1000010001 20001X0011 4001XX0101 801XXX0111 161XXXX1001

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Chapter 4 14 Priority Encoder Example (continued) Could use a K-map to get equations, but can be read directly from table and manually optimized if careful: A 2 = D 4 A 1 = D 3 + D 2 = F 1, F 1 = (D 3 + D 2 ) A 0 = D 3 + D 1 = (D 3 + D1) V = D 4 + F 1 + D 1 + D 0 D4D4 D3D3 D4D4 D4D4 D4D4 D3D3 D4D4 D2D2 D4D4 D2D2

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Chapter 4 15 Selecting of data or information is a critical function in digital systems and computers Circuits that perform selecting have: A set of information inputs from which the selection is made A single output A set of control lines for making the selection Logic circuits that perform selecting are called multiplexers Selecting can also be done by three-state logic or transmission gates Selecting

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Chapter 4 16 Multiplexers A multiplexer selects one input line and transfers it to output n control inputs (S n 1, … S 0 ) called selection inputs m 2 n information inputs (I 2 n 1, … I 0 ) output Y

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Chapter 4 17 2-to-1-Line Multiplexer Since 2 = 2 1, n = 1 The single selection variable S has two values: S = 0 selects input I 0 S = 1 selects input I 1 The equation: Y = I 0 + SI 1 The circuit: S

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Chapter 4 18 2-to-1-Line Multiplexer (continued) Note the regions of the multiplexer circuit shown: 1-to-2-line Decoder 2 Enabling circuits 2-input OR gate To obtain a basis for multiplexer expansion, we combine the Enabling circuits and OR gate into a 2 2 AND-OR circuit: 1-to-2-line decoder 2 2 AND-OR In general, for an 2 n -to-1-line multiplexer: n-to-2 n -line decoder 2 n 2 AND-OR

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Chapter 4 19 Example: 4-to-1-line Multiplexer 2-to-2 2 -line decoder 2 2 2 AND-OR

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Chapter 4 20 Multiplexer Width Expansion Select “vectors of bits” instead of “bits” Use multiple copies of 2 n 2 AND-OR in parallel Example: 4-to-1-line quad multi- plexer

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Chapter 4 21 Other Selection Implementations Three-state logic in place of AND-OR Gate input cost = 14 compared to 22 (or 18) for gate implementation

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Chapter 4 22 Other Selection Implementations Transmission Gate Multiplexer Gate input cost = 8 compared to 14 for 3-state logic and 18 or 22 for gate logic

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Chapter 4 23 Summary Functions and functional blocks Enabling Decoding Encoding Selecting with multiplexers

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Chapter 4 24 Terms of Use © 2004 by Pearson Education,Inc. All rights reserved. The following terms of use apply in addition to the standard Pearson Education Legal Notice.Legal Notice Permission is given to incorporate these materials into classroom presentations and handouts only to instructors adopting Logic and Computer Design Fundamentals as the course text. Permission is granted to the instructors adopting the book to post these materials on a protected website or protected ftp site in original or modified form. All other website or ftp postings, including those offering the materials for a fee, are prohibited. You may not remove or in any way alter this Terms of Use notice or any trademark, copyright, or other proprietary notice, including the copyright watermark on each slide. Return to Title Page Return to Title Page

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