1. 1 Combinational Logic EE 208 – Logic Design Chapter 4 Sohaib Majzoub

2. 2 What is a Combinational network? Combinational Network X1X1 XmXm X2X2 Z1Z1 ZmZm Z2Z2 Combinational Network: A stateless network (it does not have a memory). The output is completely determined by the values of the input. Output at time t depends only on input at time t Sequential Network: The network stores an internal state. The output is determined by the input, and by the internal state. (it has a memory) Output at time t depends on input at time t and output at time t-1

3. 3 Combinational Circuits Analysis and Design Analysis –Given a circuit, find out its function –Function may be expressed as: Boolean function Truth table Design –Given a desired function, determine its circuit –Function may be expressed as: Boolean function Truth table ? ? ?

4. 4 Analysis Procedure Boolean Expression Approach T 2 =ABC T 1 =A+B+C F 2 =AB+AC+BC F’ 2 =(A’+B’)(A’+C’)(B’+C’) T 3 =AB'C'+A'BC'+A'B'C F 1 =AB'C'+A'BC'+A'B'C+ABC F 2 =AB+AC+BC

5. 5 Analysis Procedure Truth Table Approach A B C F1F1 F2F2 0 0 0 = 0 0000000000 0 1 0 0 0

6. 6 Analysis Procedure Truth Table Approach = 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 0100001000 0 1 1 1 A B C F1F1 F2F2 0 0 000 0 0 1 1 0

7. 7 Analysis Procedure Truth Table Approach = 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 = 0 0100001000 0 1 1 1 A B C F1F1 F2F2 0 0 000 0 0 110 0 1 0 1 0

8. 8 Analysis Procedure Truth Table Approach = 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 0100101001 1 0 0 0 A B C F1F1 F2F2 0 0 000 0 0 110 0 1 010 0 1 1 0 1

9. 9 Analysis Procedure Truth Table Approach = 1 = 0 = 1 = 0 = 1 = 0 = 1 = 0 0100001000 0 1 1 1 A B C F1F1 F2F2 0 0 000 0 0 110 0 1 010 0 1 101 1 0 0 1 0

10. Analysis Procedure Truth Table Approach = 1 = 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 0101001010 1 0 0 0 A B C F1F1 F2F2 0 0 000 0 0 110 0 1 010 0 1 101 1 0 010 1 0 1 0 1

11. 11 Analysis Procedure Truth Table Approach = 1 = 0 = 1 = 0 = 1 = 0 = 1 = 0 0110001100 1 0 0 0 A B C F1F1 F2F2 0 0 000 0 0 110 0 1 010 0 1 101 1 0 010 1 0 101 1 1 0 0 1

12. 12 Analysis Procedure Truth Table Approach = 1 1111111111 1 0 0 1 A B C F1F1 F2F2 0 0 000 0 0 110 0 1 010 0 1 101 1 0 010 1 0 101 1 1 001 1 1 1 1 B 0101 A1010 C B 0010 A0111 C F 1 =AB'C'+A'BC'+A'B'C+ABC F 2 =AB+AC+BC

13. 13 Design Procedure Given a problem statement: –Determine the number of inputs and outputs –Derive the truth table –Simplify the Boolean expression for each output –Produce the required circuit Example: Design a security alarm circuit: ?

14. 14 Design Example Design a circuit to convert a “BCD” code to “Excess 3” code

15. 15 Design Example BCD-to-Excess 3 Converter A B C D w x y z 0 0 0 0 1 1 0 0 0 10 1 0 0 0 0 1 00 1 0 0 1 10 1 1 0 0 1 0 00 1 1 1 0 1 1 0 0 0 0 1 1 01 0 0 1 0 1 1 11 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 1 0 x x 1 0 1 1x x 1 1 0 0x x 1 1 0 1x x 1 1 1 0x x 1 1 x x C 111 B A xxxx 11 xx D C 111 1 B A xxxx 1 xx D C 11 11 B A xxxx 1 xx D C 11 11 B A xxxx 1 xx D w = A+BC+BDx = B’C+B’D+BC’D’ y = C’D’+CDz = D’

16. 16 Design Procedure BCD-to-Excess 3 Converter A B C D w x y z 0 0 0 0 1 1 0 0 0 10 1 0 0 0 0 1 00 1 0 0 1 10 1 1 0 0 1 0 00 1 1 1 0 1 1 0 0 0 0 1 1 01 0 0 1 0 1 1 11 0 1 0 0 01 0 1 1 1 0 0 11 1 0 0 1 0 x x 1 0 1 1x x 1 1 0 0x x 1 1 0 1x x 1 1 1 0x x 1 1 x x w = A + B(C+D) x = B’(C+D) + B(C+D)’ y = (C+D)’ + CD z = D’

17. 17 More Blocks: Binary Adders Half Adders: adds 2 1-bit operands (x and y) to produce 2-bit result (a carry and a sum) Sum = S = a’b+ab’ = a  b Carry = C = ab

18. 18 Half Adders Example: built a four bit adder using Half adders only. Half adders doesn’t consider the previous carry => need to include carry-in

19. 19 Full Adders Carry is included as another input => 3 inputs and 2 outputs: ab 1 0 2 4 3 5 6 7 C in 0 1 00011110 1 11 1 ab 1 0 2 4 3 5 6 7 C in 0 1 00011110 1 1 1 1 SUM C out

20. 20 Full Adders 1-bit Full adder: S = a  b  C in C out = a b+a C in +b C in 4-bit full adder: 4 cascaded (connecting one after the other) full adders, called ripple adder.

21. 21 Ripple Adder The carry has to propagate (ripple) through all adders, Next adder has to wait for carry-in from previous adder, delay of two gates (AND-OR) per adder => 4-bit adder => 8 gate delay. What about 64-bit adder => 128 gate delay=> delay is too high. Ripple adder rarely used.

22. 22 Carry Look Ahead Adder Attempt to generate the carry-in using a separate logic, eliminate waiting time (does not wait for the previous adder to generate the carry). Carry Generate: for a particular combination of inputs a i and b i, adder stage i is said to generate a carry if it produces carry-out of 1 (c i+1 =1) independent of the inputs a 0 -a i-1, b 0 -b i-1, and c 0 Carry Propagate: for a particular combination of inputs a i and b i, adder stage i is said to propagate carries if it produces carry-out of 1 (c i+1 =1) in the presence of the input combination a 0 -a i-1, b 0 -b i-1, and c 0 that causes a carry-in of 1 (c i =1)

23. 23 To realize the propagate and generate cases, we introduce two functions as shown: Back to the carry equation: C i+1 = (a i.b i )+(a i +b i ).C i = g i + p i.C i 0 0 0 0 0 00 0 0 1 01 00 0 1 0 01 00 0 1 1 10 01 1 0 0 01 00 1 0 1 10 01 1 1 0 10 10 1 1 1 11 11 Carry Look Ahead Adder a b C in C out S propagate generate G P.C in

24. 24 Carry Look Ahead Adder C i+1 = (a i.b i )+(a i +b i ).C i = g i + p i.C i => Stage 0: C 1 = g 0 + p 0.C 0 = (a 0.b 0 )+(a 0 +b 0 ).C 0 Stage 1: C 2 = g 1 + p 1.C 1 = (a 1.b 1 )+(a 1 +b 1 ).C 1 =g 1 +p 1.g 0 +p 1. p 0.C 0 Stage 2: C 3 = g 2 + p 2.C 2 =g 2 + p 2.(g 1 + p 1.C 1 ) = g 2 +p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0.C 0 Stage 3: C 4 = g 3 + p 3.C 3 =g 3 + p 3.(g 2 + p 2.C 2 ) = g 3 + p 3.(g 2 + p 2.(g 1 + p 1.(g 0 + p 0.C 0 ) )) = g 3 + p 3 g 2 +p 3 p 2 g 1 +p 3 p 2 p 1 g 0 +p 3 p 2 p 1 p 0 C 0

25. 25 Carry Look Ahead Adder Basically we will add a separate hardware to break up dependency between sum and carry => duplicating logic area Still suffer from gates with large number of inputs => increasing Fan-In (more inputs) => larger transistors => higher power consumption and slower.

26. 26 Ripple Carry and CLA

27. 27CLA

28. 28 CLA Adders Use a combination of CLA Adders and Ripple Adders, Optimization between delay, power and area can take place here to find the optimal size of the CLA Adders.

29. 29 Cascaded CLA Adders Example: 16-bit Adder, then cascade 4 CLA Adders of 4-bit size.

30. 30 Binary Subtractor Use 2’s complement with binary adder –x – y = x + (-y) = x + y’ + 1

31. 31Adder/Subtractor The M signal has to be 1 when subtraction operation is needed and 0 if addition is needed:

32. 32 BCD Adder 4-bits plus 4-bits Operands and Result: 0 to 9 + x 3 x 2 x 1 x 0 + y 3 y 2 y 1 y 0 ──────── Cy S 3 S 2 S 1 S 0 X +Y x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 SumCyS 3 S 2 S 1 S 0 0 + 00 0 = 000 0 0 + 10 0 0 0 0 1= 100 0 0 1 0 + 20 0 0 0 1 0= 200 0 1 0 0 + 90 0 1 0 0 1= 901 0 0 1 1 + 00 0 0 10 0 = 100 0 0 1 1 + 10 0 0 1 = 200 0 1 0 1 + 80 0 0 11 0 0 0= 901 0 0 1 1 + 90 0 0 11 0 0 1= A01 0 2 + 00 0 1 00 0 = 200 0 1 0 9 + 91 0 0 1 = 1210 0 1 0 Invalid Code Wrong BCD Value 0001 1000

33. 33 BCD Adder X +Yx 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 SumCyS 3 S 2 S 1 S 0 Required BCD OutputValue 9 + 01 0 0 10 0 = 901 0 0 10 0 0 0 1 0 0 1= 9 9 + 11 0 0 10 0 0 1= 1001 0 0 0 0 1 0 0 0 0= 16 9 + 21 0 0 10 0 1 0= 1101 0 1 10 0 0 1 = 17 9 + 31 0 0 10 0 1 1= 1201 1 0 00 0 0 1 0 0 1 0= 18 9 + 41 0 0 10 1 0 0= 1301 1 0 10 0 0 1 0 0 1 1= 19 9 + 51 0 0 10 1 = 1401 1 1 00 0 0 1 0 1 0 0= 20 9 + 61 0 0 10 1 1 0= 1501 1 0 0 0 1 0 1 0 1= 21 9 + 71 0 0 10 1 1 1 = 1610 0 0 0 0 1 0 1 1 0= 22 9 + 81 0 0 11 0 0 0 = 1710 0 0 10 0 0 1 0 1 1 1= 23 9 + 91 0 0 1 = 1810 0 1 00 0 0 1 1 0 0 0= 24 + 6 

34. 34 BCD Adder Correct Binary Adder’s Output (+6) –If the result is between ‘A’ and ‘F’ –If Cy = 1 S 3 S 2 S 1 S 0 Err 0 0 0 1 0 0 00 1 0 0 10 1 0 1 1 0 1 11 1 1 0 01 1 1 0 11 1 1 1 01 1 1 1 S1S1 S2S2 S3S3 1111 11 S0S0 Err = S 3 S 2 + S 3 S 1

35. 35 BCD Adder Err

36. 36 Overflow Unsigned Binary Numbers 2’s Complement Numbers FA x 3 x 2 x 1 x 0 FA y 3 y 2 y 1 y 0 S 3 S 2 S 1 S 0 C 4 C 3 C 2 C 1 0 Carry FA x 3 x 2 x 1 x 0 FA y 3 y 2 y 1 y 0 S 3 S 2 S 1 S 0 C 4 C 3 C 2 C 1 0 Overflow

37. 37  Binary Multiplier ●Two 2-bit numbers (A=A 1 A 0 ) and (B=B 1 B 0 ). X0X0 X0X0 X1X1 X1X1 X2X2 X2X2 X3X3 X3X3

38. 38  Binary Multiplier ●Two binary numbers : ●J multiplier bits ●K multiplicand bits.  We need: ●(J  K) AND gates. ●(J  1) K-bit adders

39. 39  Binary Multiplier B0B0 B2B2 B1B1 A0A0 A0B0A0B0 _________________________________ A1A1 A2A2 A0B1A0B1 B3B3 A0B2A0B2 A0B3A0B3 A1B0A1B0 A1B1A1B1 A1B2A1B2 A1B3A1B3 A2B0A2B0 A2B1A2B1 A2B2A2B2 A2B3A2B3 _____________________________________ Z0Z0 Z2Z2 Z1Z1 Z3Z3  __________________________________________________ Z4Z4 + + C0C0 C2C2 C1C1 C3C3 C4C4 C5C5 C6C6 J = 3 K = 4 AND gates (12 gates) 4-bit Adder (2 units) 0

40. 40  Binary Multiplier Z0Z0 Z2Z2 Z1Z1 Z3Z3 Z4Z4

41. 41 Decoders and Encoders A code is a string of several bits, with an n-bit code, it is possible to represent 2 n. A decoder translate the n- bit pattern into a specific code of 2 n possible values. A decoder translate a binary value into a non-binary output. An encoder, translate a non-binary value into a binary value. An n-input decoder has n-inputs and 2 n outputs

42. 42Decoders One-hot encoding (only one output high at a time) Example: a 3-bit binary to decimal decoder, called 3- to-8 decoder.

43. 43 Functions using Decoders We can implement functions using decoders. Example: F(A,B,C) = Σ m (1,3,7) and G(A,B,C) = Σ m (2,3,6) using decoder Less efficient than our optimized AND-OR logic, but sometimes used in small circuits (MSI).

44. 44 Decoder-Based Adder One decoder to implement a full adder with sum and carry output. C = Σm(3,5,6,7) and S =Σm(1,2,4,7)

45. 45 Code Conversion Decoders are also used for code conversion, Example code conversion can be: -BCD-to-7 segment display -BCD-to-decimal -BCD-to-Gray -Binary-to-Gray

46. 46 BCD-to-7 segment display Example

47. 47 Cascading Decoders 3-to-8 decoder requires 8 gates 4-t0-16 requires 16 gates 5-to-32 requires 32 gates Number of gates increases exponentially with number of inputs. You might not need all outputs (BCD-to- decimal) Cascade decoders and use only the required number of outputs

48. 48 Building 3-8 out of 2-4 Decoders Another way to design a decoder is to break it into smaller decoders: –When S2 = 0, outputs Q0-Q3 are generated as in a 2-to-4 decoder. –When S2 = 1, outputs Q4-Q7 are generated as in a 2-to-4 decoder. Q0= S2’ S1’ S0’= m 0 Q1= S2’ S1’ S0= m 1 Q2= S2’ S1 S0’= m 2 Q3= S2’ S1 S0= m 3 Q4= S2 S1’ S0’= m 4 Q5= S2 S1’ S0= m 5 Q6= S2 S1 S0’= m 6 Q7= S2 S1 S0= m 7

49. 49 3-8 Decoder Enable input used to select lower or higher nibble:

50. 50 Cascading Decoders 4-to-16 decoder made of 2x 3-to-8 decoders

51. 51 Active-Low Decoder So far we looked at active high decoders. Active-low decoders are similar but with inverted input and outputs

52. 52 Active Low Decoders An active low 2-to-4 decoder with enable, Active Low => use Maxterms: D 0 = E+A+B =(E’.A’.B’)’; D 1 = E+A+B’ =(E’.A’.B)’; D 2 = E+A’+B =(E’.A.B’)’; D 3 = E+A’+B’ =(E’.A.B)’; Using NAND will convert Maxterms to minterms

53. 53 Active Low Decoders Active-low decoders generate Maxterms Example: f(x,y,z)= ΠM(4,5,7) Use a NAND to generate minterms Q3’= (S1 S0)’ = S1’ + S0’ Q2’= (S1 S0’)’ = S1’ + S0 Q1’= (S1’ S0)’ = S1 + S0’ Q0’= (S1’ S0’)’ = S1 + S0

54. 54Encoders An encoder performs the reverse function of a decoder => has fewer outputs to inputs. A binary encoder has 2 n -n input to output. Usually only one input is 1 the rest is zero.

55. 55 Example: 8-to-3 Encoder Only one input at a time is high, the rest is zero, Idle = I 7 ’. I 6 ’. I 5 ’. I 4 ’. I 3 ’. I 2 ’. I 1 ’. I 0 ’ Valid = I 7 + I 6 + I 5 + I 4 + I 3 + I 2 + I 1 + I 0 000000010000000010 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 Y 2 Y 1 Y 0 Idle Valid 000000100000000100 000001000000001000 000010000000010000 000100000000100000 001000000001000000 010000000010000000 100000000100000000 00001111x00001111x 00110011x00110011x 01010101x01010101x 000000001000000001 111111110111111110

56. 56 Priority Encoders The assumption of having a single input as a one and the rest are zeros might be violated (sending multiple interrupt requests to the encoder in a micro- processor). Example: I 2 and I 4 are one which it will produce Y 2 Y 1 Y 0 = 110 (it should’ve been either 010 or 100) Priority encoder ensures this never happen by assigning priority to the input lines. Thus, if more than one input is high, the encoder produces the proper binary output associated with the input that has the highest priority.

57. 57 Priority Encoders Introduce an intermediate function H’s: 010000000010000000 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 0x10000000x1000000 0xx1000000xx100000 0xxx100000xxx10000 0xxxx10000xxxx1000 0xxxxx1000xxxxx100 0xxxxxx100xxxxxx10 0xxxxxxx10xxxxxxx1 A 2 A 1 A 0 Idle x11110000x11110000 x11001100x11001100 x10101010x10101010 100000000100000000 010000000010000000 H 7 H 6 H 5 H 4 H 3 H 2 H 1 H 0 001000000001000000 000100000000100000 000010000000010000 000001000000001000 000000100000000100 000000010000000010 000000001000000001

58. 58 Priority Encoder Example: I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 = 00100100 => I 5 is higher priority than I 2 => H 7 H 6 H 5 H 4 H 3 H 2 H 1 H 0 = 00100000 => A 2 A 1 A 0 = 101

59. 59 Multiplex the inputs and pass one or more signal to the output using a selector. 2 n inputs to one output with n selectors. Multiplexers: Data Selector

60. 60Multiplexers 4-to-1 Multiplexer: Y = S 1 ’.S 0 ’.X 0 + S 1 ’.S 0.X 1 +S 1.S 0 ’.X 2 +S 1.S 0.X 3 00110011 S 1 S 0 Y 01010101 X0 X1 X2 X3

61. 61 4-ways Multiplexer Output = Minterm. Input Out = m0.W+m1.X+m2.Y+m3.Z Out = S1’.S0’.W+S1’.S0.X+S1.S0’.Y+S1.S0.Z 00110011 S 1 S 0 out 01010101 WXYZWXYZ

62. 62 Bus Multiplexing Multiplexing a bus of MxN data lines into N data lines. Needs M selectors Output Bus A or Bus B Each bus is 4-bit wide

63. 63 Build Multiplexers Using Decoders Use a decoder to generate the minterms

64. 64 Building Logic Functions Using MUXs The variables has to be split into inputs and selectors of the multiplexer. A common way to use n-1 as selectors and the remaining variable with its complement as an input. Example: given the function: F(A,B,C) = Σm(2,3,5,7) To be implemented using 8-to-1 multiplexer

65. 65 Building Logic Functions Using MUXs F(A,B,C) = Σm(2,3,5,7)

66. 66 Building Logic Functions Using MUXs F(A,B,C) = Σm(2,3,5,7) Using 4-to-1 MUX

67. 67 Building Logic Functions Using MUXs Example: F(A,B,C) = Σm(1,3,5,6) Can you use 4-to-1 MUX? 2 variables as selectors

68. 68 Building Logic Functions Using MUXs Example: implement the following function using 8-to-1 MUX: 4-to-1 MUX?

69. 69 Designing Using MUXs Design an Adder/ Subtractor using MUXs and a single Adder to that can do the following operations: A-B, -A+B, B-A, -B+A

70. 70Demultiplexer One input to 2 n outputs with n selectors Y 0 = S 1 ’.S 0 ’.X Y 1 = S 1 ’.S 0.X Y 2 = S 1.S 0 ’.X Y 3 = S 1.S 0.X similar to decoders? 00110011 S 1 S 0 Y 0 Y 1 Y 2 Y 3 01010101 X000X000 0X000X00 00X000X0 000X000X

71. 71 Tri-State Buffer A Tri-state buffer can output either 1, 0, or high impedance.

72. 72Comparators Inputs A and B each of n-bits Output is 1 if A=B A>B A<B and 0 if A≠B 00110011 A 0 B 0 A 0 =B 0 01010101 10011001

73. 73Comparators Output 1 if A> B and 0 otherwise 00110011 A 0 B 0 A 0 >B 0 01010101 00100010