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Logic Design (CE1111 ) Lecture 4 (Chapter 4) Combinational Logic Prepared by Dr. Lamiaa Elshenawy 1.

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Presentation on theme: "Logic Design (CE1111 ) Lecture 4 (Chapter 4) Combinational Logic Prepared by Dr. Lamiaa Elshenawy 1."— Presentation transcript:

1 Logic Design (CE1111 ) Lecture 4 (Chapter 4) Combinational Logic Prepared by Dr. Lamiaa Elshenawy 1

2 Outlines  Combinational Circuits  Analysis Procedure  Design Procedure  Binary Adder-Subtractor  Decimal Adder  Binary Multiplier  Magnitude Comparator  Decoders  Encoders  Multiplexers 2

3 3 o consists of logic gates o outputs are determined from only the present combination of inputs o consists of logic gates and storage elements o outputs are determined from the present combination of inputs & past inputs Logic Circuits Combinational Circuits Sequential Circuits Logic Circuits

4 Combinational Circuits 4

5 Analysis Procedure 5  How analyze combinational circuits? 1. Label all gate inputs & outputs with arbitrary symbols 2. Determine the Boolean functions for each gate output 3. Repeat step 2 until the outputs of the circuit are obtained 4. Determine the output Boolean functions in terms of input variables

6 Analysis Procedure 6

7 7

8  How derive a truth table for a combinational circuit? 1. Write the input variables and their possible binary number combinations and list the binary numbers from 0 to (2n - 1) 2. Obtain the truth table for the outputs of logic gates 3. Repeat step 2 until the outputs of the circuit are obtained 8

9 Design Procedure  How design combinational circuits? 1. Determine the required number of inputs and outputs and assign a symbol to each 2. Derive the truth table that defines the required relationship between inputs and outputs 3. Obtain the simplified Boolean functions for each output as a function of the input variables 4. Draw the logic diagram and verify the correctness of the design (manually or by simulation) 9

10 Example 1  Design a combinational circuit to convert from BCD into excess-3 code.  Solution: 10

11 Example 1 (Contd.) 11

12 Example 1 (Contd.) 12

13 Example 1 (Contd.) 13

14 Binary Adder-Subtractor  What is Binary Adder-Subtractor?  A binary Adder–Subtractor is a combinational circuit that performs the arithmetic operations of addition and subtraction with binary numbers 14

15 Binary Adder 15 Half Adder Add 2 variables Full Adder Add 3variables

16 Binary Adder 16 Half Adder Implementation

17 Binary Adder 17 Full Adder Implementation

18 Binary Adder  Is there another way to implement Full Adder? 18

19 Binary Adder 19

20 Example 2 (Contd.) 20 Four-bits Adder

21 Binary Subtractor  How subtract two binary numbers with n-bits?  It can be done using full adder connected in cascade with X- OR logic gates  Example 2: Subtract the following two binary numbers A and B  Solution o Unsigned numbers A - B if A> B or 2’s complement of (B – A) if A < B (determine the 1’s complement and then add 1) o Signed numbers 21 A-BNo overflow

22 Binary Subtractor 22

23 Binary Subtractor 23

24 BCD Adder  BCD adder is a combinational circuit that add decimal numbers  BCD adder requires 1. nine inputs 2. five outputs(four bits for each decimal digit, one bit input and output carry)  Each input digit does not exceed 9, the output sum cannot be greater than 9 + 9 + 1 = 19,  the 1 in the sum being an input carry 24

25 Decimal Adder 25

26 26

27 BCD Adder  When C = 1, it is necessary to add 0110 to the binary sum and provide an output carry for the next stage 27

28 Binary Multiplier  Multiplication of binary numbers is performed in the same way as multiplication of decimal numbers 1. The multiplicand is multiplied by each bit of the multiplier, starting from the least significant bit 2. Each such multiplication forms a partial product 3. Successive partial products are shifted one position to the left 4. The final product is obtained from the sum of the partial products 28

29 Binary Multiplier 29 multiplicand multiplier

30 Binary Multiplier  For J multiplier bits and K multiplicand bits, we need: 1. (J x K) AND gates 2. (J – 1) K-bit adders to produce a product of 3. (J + K) bits 30

31 31

32 Magnitude Comparator  A magnitude comparator is a combinational circuit that compares two numbers A and B. The outcome of the comparison is specified by three binary variables 1. A = B 2. A > B 3. A < B 32

33 Magnitude Comparator 33

34 Magnitude Comparator 34

35 Decoders 35

36 Decoders 36 Three-to-eight-line decoder

37 Decoders 37

38 Decoders 38 Two-to-four-line decoder with enable input

39 Decoders 39 4 x16 decoder constructed with two 3 x 8 decoders

40 Decoders 40 Implementation of a full adder with a decoder

41 Encoder 41

42 Encoder 42

43 Priority Encoder 43  A priority encoder is an encoder circuit that includes the priority function  the higher the subscript number, the higher the priority of the input High subscript

44 Priority Encoder 44 Maps for a priority encoder

45 Priority Encoder 45 Four- input priority encoder

46 Multiplexers 46

47 Multiplexers 47 Two-to-one-line multiplexer

48 Multiplexers 48 Four-to-one-line multiplexer

49 Multiplexers 49

50 Multiplexers 50 Example 1:

51 Multiplexers 51 Example 2:

52 52


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