1. Decoders, Encoders, Multiplexers
Ege University
Department of Computer Engineering
Decoders, Encoders, Multiplexers
BIL- 223 Logic Circuit Design

2. Decoding Decoding - the conversion of an n-bit input code to
an m-bit output code with
n £ m £ 2n
such that each valid code word produces a unique
output code
Circuits that perform decoding are called decoders
Functional blocks for decoding are called
n-to-m line decoders
where m £ 2n, and generate 2n (or fewer) minterms for
the n input variables

3. 1-to-2-Line Decoder A D1 D0 1 D0 A D1

4. 2-to-4-Line Decoder 2-to-4 -line decoder D0 A1 A0 D3 D2 D1 D0 1 A0 D11
2-to-4
-line
decoder A0 D1 D2 A1 D3

5. 2-to-4-Line Decoder A1 A0 D3 D2 D1 D0 1 A1 A0 D0 D1 D2 D3

6. Enabling Enabling permits an input signal to pass through to an output
Disabling blocks an input signal from passing through to an output, replacing it with a fixed value

7. 2-to-4-Line Decoder w/ EnableX 1 D0 D1 D2 D3
2-to-4
-line
decoder A0 A1 En

8. 2-to-4-Line Decoder w/ EnableX 1 A1 A0

9. 3-to-8-Line Decoder
Truth Table A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1

10. 3-to-8-Line Decoder (1)

11. 3-to-8-Line Decoder
Truth Table A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1

12. 3-to-8-Line Decoder (2) D0 A0 A0 2-to-4 D1 -line decoder A1 D2 A1 D3En A0 A1 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1 A2 D0 D1 D2 D3
2-to-4
-line
decoder A0 A1 En D4 D5 D6 D7

13. Implementing Combinational Logic with DecoderF1 Z A0
3-to-8
-line
decoder D2 Y A1 D3 D4 X A2 F2 D5 D6 D7

14. Encoding
Encoding - the opposite of decoding - the conversion of an m-bit input code to a n-bit output code with n £ m £ 2n such that each valid code word produces a unique output code
Circuits that perform encoding are called encoders
An encoder has 2n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values

15. M-to-N-Line Encoder (M2N)
Decoder A0 A1 En D0
4-to-2
-line
Encoder A0 D1 D2 A1 D3 Ac

16. 4-to-2 Encoder For A0 For A1 Since Dx=1 only in one column at a time
D1 D0
For A0 00 01 11 10 X 1
D3 D2 D3 D2 D1 D0 A1 A0 1
D1 D0
For A1
D3 D2 00 01 11 10 X 1
Since Dx=1 only in one column at a time
A0 = D1 + D3
A1 = D2 + D3

17. 8-to-3 Encoder Since Dx=1 only in one column at a time1
Since Dx=1 only in one column at a time
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7

18. Priority Encoder
If more than one input value is 1, then the encoder just designed does not work.
One encoder that can accept all possible combinations of input values and produce a meaningful result is a priority encoder.
Among the 1s that appear, it selects the most significant input position (or the least significant input position) containing a 1 and responds with the corresponding binary code for that position.

19. 8-to-3 Priority Encoder D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
Active 1 X

20. 4-to-2 Priority Encoder For A1 Or using simplification property D1 D0
Active 1 X 00 01 11 10 1
D3 D2
Or using simplification property

21. 4-to-2 Priority Encoder For A0 Or using simplification property D1 D0
Active 1 X 00 01 11 10 1
D3 D2
Or using simplification property

22. 4-to-2 Priority Encoder For Active D1 D0 D3 D2 D3 D2 D1 D0 A1 A01 X 00 01 11 10 1
D3 D2

23. 4-to-2 Priority Encoder Schematic
Active

24. 8-to-3 Priority Encoder (A2)
Active 1 X

25. 8-to-3 Priority Encoder (A1)
Active 1 X

26. 8-to-3 Priority Encoder (A0)
Active 1 X

27. 8-to-3 Priority Encoder (All)
Active 1 X

28. Selecting
Selecting of data or information is a critical function in digital systems and computers
Circuits that perform selecting have:
A set of information inputs from which the selection is made
A single output
A set of control lines for making the selection
Logic circuits that perform selecting are called multiplexers

29. Multiplexers
A multiplexer selects information from an input line and directs the information to an output line
A typical multiplexer has n control inputs (Sn - 1, … S0) called selection inputs, 2n information inputs (I2n - 1, … I0), and one output Y
A multiplexer can be designed to have m information inputs with m < 2n as well as n selection inputs

30. Multiplexers (Mux) Functionality: Selection of a particular input
Route 1 of N inputs (A) to the output F
Require selection bits (S)
En(able) bit can disable the route and set F to 0 F A0 A1 A2 A3 S1 S0 En
4-to-1
Mux

31. Multiplexers (Mux) w/out EnableF A0 1 A1 A2 A3 A0 A1 F
4-to-1
Mux A2 A3 S1 S0

32. Logic Diagram of a 4-to-1 Mux (1)S1 S0 F A0 A1 A2 A3

33. Logic Diagram of a 4-to-1 Mux (2)
2-to-22-line decoder
22 ´ 2 AND-OR x

34. Multiplexers (Mux) w/ EnableF A0 A1 A2 A3 S1 S0 En
4-to-1
Mux En S1 S0 F X 1 A0 A1 A2 A3

35. 4-to-1 Mux w/ Enable LogicS1 S0 F En A0 A1 A2 A3

36. 4-to-1 Mux w/ Enable LogicS1 S0 En F A0 A1
Reduce one Gate Delay
by using 4-input
AND gate for the 2nd
level A2 A3 En

37. Quadruple 2-to-1 Line MuxEn
A[3:0]
A3..0
2-to-1
Mux
F[3:0] En
SEL
F[3:0] X
0000 1
A[3:0]
B[3:0]
B3..0
B[3:0]
SEL

38. Quadruple 2-to-1 Line MuxF0 B1 A1 F1
Fx=Ax·En·SEL+Bx·En·SEL B2 A2 F2 B3 A3 F3 En
SEL
F[3:0] X
0000 1
A[3:0]
B[3:0]
SEL B0 En

39. Combinational Logic Implementation with Multiplexers
Each input in a MUX is a minterm F A0 A1 A2 A3 S1 S0
8-to-1
Mux S2 A4 A5 A6 A7 1 1 1 1 A B C

40. Combinational Logic Implementation with MultiplexersF 1

41. Combinational Logic Implementation with MultiplexersF C 1 C En A0 C A1 F
4-to-1
Mux A2 1 A3
5 V S1 S0 A B

42. Combinational Logic Implementation with MultiplexersF 1

43. Combinational Logic Implementation with MultiplexersF 1 A En A0 A1 A F
4-to-1
Mux 5V A2 A A3 S1 S0 B C

44. Design Example: Gray to Binary Code
Design a circuit with multiplexers
to convert a 3-bit Gray code to
a binary code
Gray
A B C
Binary
x y z
1 0
0 1 1
0 1 0
1 0 1

45. Demultiplexers (DeMux)F A0 A1 A2 A3 S1 S0
4-to-1
Mux D0 D1
1-to-4
DeMux A D2 D3 S1 S0

46. DeMux Operations 1-to-4 DeMux S1 S0 D3 D2 D1 D0 A 1 D0 D1 A D2 D3 S1A 1 D0 D1
1-to-4
DeMux A D2 D3 S1 S0

47. DeMux Operations S1 S0 D3 D2 D1 D0 A 1 D0 D1 D2 D3 A S1 S0

48. DeMux Operations w/ EnableX 1 A

49. Other Selection Implementations
Three-state logic in place of AND-OR
Gate input cost = 14 compared to 22 (or 18) for gate implementation