LAV firmware status Francesco Gonnella Mauro Raggi 28 th March 2012 TDAQ Working Group Meeting

PP firmware framework 28 March 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy2

LAV firmware tasks  Produce a specific data stream for trigger primitive generation  Time correction (PP)  Constant offset  Slewing  Trigger and fine time generation (SL)  Collect signals into physical events  Calculate fine time as the average of selected-block times All time corrections shall be used for trigger purpose only. Data stored on DDR will be untouched. 28 March 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy3

Input data-stream (1/2)  Data-stream characteristics  Transmission frequency: 160 MHz  32-bit words: Flag (31:28) - Channel (27:19) - Measure(18:0)  Flags: 0xA Timestamp, 0xB Footer, 0x4 Leading, 0x5 Trailing  Time measurement LSB ~100 ps  Timestamp characteristics  Timestamp LSB ~ 400 ns  Timestamp is a 28-bit word  Timestamp is transmitted every ~12.8 μs, i.e. four times before fine-time rollover  This periodicity could be subject to modifications 28 March 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy4

Input data-stream (2/2) TimestampFine time  7-bit overlap between Timestamp and Fine time  Possibility of data rollover before next time-stamp 28 March 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy ps ns μs ms Maximum time ~ 1 s 0xA xA

Framework  Project developed with HDL Designer  Behavioural simulation performed with ModelSim  Synthesis performed with Quartus II within HDL Designer  Not using Tell1 framework and libraries  Using an independent test-bench  Data-stream coming from custom text file 28 March 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy6

LAV firmware architecture 28 March 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy7 InputOutput ClockStrobe Out ResetBlock Number (5:0) Strobe InRise Time (7:0) Data In (31:0)Time Out (39:0) RAM Address (8:0) RAM Data (12:0) RAM WE  Offset corrector;  RAM  Channel Selector  Channel FIFO (128 instances)  Priority encoder  Data demultiplexer  Event Finder FSM

Time-Offset corrector module  Receives input stream  Checks if data is time  Retrieves the proper offset value from offset RAM  Adds the offset to the time  If data is timestamp or footer  Transmits data untouched  Input-output delay: 4 clock cycles.  Offset values can be set independently for each LAV station 28 March 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy8 Data in Time Offset Corrector Data out address offset clock Strobe in Read enable RAM address offset Write enable ECS Strobe Out

Event-finder module architecture 28 March 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy9 This module works under the assumption that data, for a given channel, are time ordered.

Channel module  Data formatting  Time Stamp and rollover handling  Automatically push useless data 28 March 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy10 MegaWizard Fifo (16 words) Push Fifo Ready Empty

Test bench  Data-stream has been generated through a Toy MC code  Physical muon-hit generation with proper rate (~1 MHz)  Poissonian pulse-height generation according to LAV specs  H&L threshold (7 and 25 mV) crossing-time evaluation  TDCB-like data stream production dumped to an ASCII file  Behavioural VHDL simulation  Stand-alone test bench (not within TELL1 framework)  Read data stream from ASCII file  Write output data to ASCII file  Post-synthesis simulation (within HDL designer)  Found some “bug” in HDL generation, contact me for details  Exactly the same results as behavioural 28 March 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy11

Test-bench results 28 March 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy12 eventoutput data14 clock cycles 18 clk 550 clk460 clk  First output data is generated 14 clock cycles after the first complete (high and low threshold crossing) event is received  Data received in 570 clock cycles (3.6 μs) are managed after 460 clock cycles (2.9 μs).

Preliminary FPGA resources estimate Fitter StatusSuccessful - Fri Mar 23 11:10: Quartus II Version11.0 Build /03/2011 SP 1 SJ Full Version FamilyStratix III DeviceEP3SL110F1152C4 Logic utilization28% Combinational ALUTs17,365 / 86,000 ( 20 % ) Memory ALUTs0 / 43,000 ( 0 % ) Dedicated logic registers20,924 / 86,000 ( 24 % ) Total registers20924 Total block memory bits53,760 / 4,303,872 ( 1 % ) DSP block 18-bit elements0 / 288 ( 0 % ) Total PLLs0 / 8 ( 0 % ) Total DLLs0 / 4 ( 0 % ) 28 March 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy13

Conclusions  Status:  We have a first version of the PP firmware, up to the computational part;  A synthesis has been completed successfully;  Things to do:  Write the computational part: retrieving threshold form RAM, compute the slewing correction (one multiplication and one division)  Reduce logic utilization (we have some ideas)  Make some parameter programmable by CCPC on TEL62:  Time Stamp resolution (overlap with Fine Time)  Customisable channel mapping  Write the trigger primitive generation HDL on SL FPGA 28 March 2012Francesco Gonnella - I.N.F.N. - Laboratori Nazionali di Frascati - Italy14

Thank you for your attention 28 March