1. Jet algorithm and Jet FPGA by Attila Hidvégi

2. Content Status of the Jet algorithm New design for the Jet FPGA on JEM-1.0 Jet CMM firmware Summary Outlook

3. Status of the Jet algorithm The algorithm is working correctly. Transmission of jet multiplicity and RoI, through G-Link seems to work. However wrong events are read out. The two clock cycle version of the algorithm requires Leonardo 2002e.16 with ISE 5.2. FCAL handling will be added soon, and will require 8 more thresholds. Different threshold values will be applied to a tower, depending on whether it contains an FCAL element or not. The output format of the jet multiplicity can be reprogrammed once it has been decided how it should look like. One proposal is: 8 x 2 bit normal4 x 2 bit FCALParity

4. Jet FPGA on JEM-1.0 The code is being rewritten from scratch. New debugging features added. Needs to be configurable through registers, so we don’t need to resynthesize each time a simple modification or fine-tuning is carried out. The registers will be reconfigured with a standalone software. The same software will be used to read out all the spy memories. The design needs to have a default configuration. This could be the final design.

5. Design overview

6. Control overview

7. Jet CMM firmware Jet CMM is an extension of CP design: –16 JEMs vs. 14 CPMs –Jet-Et calculation –Separate handling of central and FCAL jets Current firmware status –Multiplicities and Jet-Et implemented for central jets (not well-tested) –FCAL jet handling currently being added

8. Summary Jet algorithm is working fine, and FCAL handling will be added soon. New Jet FPGA design is created, with many new debug features. A standalone software will be used to configure the FPGA for debug purposes.

9. Outlook The design needs to be finished. The standalone software needs to be written. The design needs to be tested and debugged in Mainz. Continue with the tests at RAL. FCAL handling needs to be added to the jet algorithm.