The System Bus

Conceptual CPU Block Diagram Datapath Regs Buses ALU Control Unit Bus Interface IR etc. PC etc. Control Signals Status Signals PSR System Bus Data Addr Control Sequencing and Timing Logic

CPU System Bus Data Addr Control

CPU System Bus Data Bus D0-D31 Address Bus A0-A31 Control Bus 32

CPU Input/ Output Memory Single-Bus System: Simplified Block Diagram Data Bus Address Bus Control Bus System Bus 32

CPU Input/ Output Memory Data Bus Address Bus Control Bus System Bus 32 Address Obj Code Source Code c2002db0 ld [x], %r db0 fffffffe x:.word -2

Read Cycle Bus Timing (Synchronous Bus) Clock (  ) Time _____ MREQ ___ RD ADDR ?Valid? ___ WR DATA Valid??

Write Cycle Bus Timing (Synchronous Bus) Clock (  ) Time _____ MREQ ___ RD ADDR ?Valid? ___ WR DATA Valid??

Address Obj Code Source Code c2002db0 ld [x], %r db0 fffffffe x:.word -2