1. 1 To write any register, we need register address and a write signal A 3-bit write address is decoded if write signal is present One of the eight registers gets a LD signal from decoder Register file design review 7 6 5 4 3 2 1 0 8-to-1 4-bit multiplex RA1 DATA1 7 6 5 4 3 2 1 0 8-to-1 4-bit multiplex RA2 DATA2 Q3 Q2 Q1 Q0 D3 D2 D1 D0 Clk LD Q3 Q2 Q1 Q0 D3 D2 D1 D0 Clk LD Q3 Q2 Q1 Q0 D3 D2 D1 D0 Clk LD LD Data WA 3 to 8 D e c o d e r WR Reg LD Signal

2. 2 ALU operation code and their meanings are –000Output A100A + B –001Output B101A - B –010Output 00..0110A and B –011Output 11..1111A or B Three bits are Sel2, Sel1, and Sel0 Sel0 makes first set of groups –Selects one of the two functions Sel2 and Sel1 selects final output –It is one of the four groups An eight function ALU design review MUX Sel0 0101 AND A B OR A B ADD/SUB A B Add/sub Result MUX 01230123 Sel2Sel1 MUX Sel0 A B MUX Sel0 0 1

3. 3 A general-purpose shift unit controls load input of the register Shift operation is controlled by two bits SC (s1 s0) as follows –00No change in register 10Shift left –01Load new data 11Shift right Thus a flip flop at position i gets its own value Q i, a new external value D i, a value on its right Q i-1, or a value on its left Q i+1 A 4-to-1 multiplexer at the input of each flip flop is thus needed For non-registered data shift unit we only need multiplexers Shifter unit review Q3 Q2 Q1 Q0 D3 D2 D1 D0 Clock SC 4-to-1 Mux Clock C D Q Q0 C D Q Q1 C D Q Q2 C D Q Q3 Q0 D3D2D1D0 Q3Q2 Q1

4. 4 A general-purpose memory has M words M is generally a power of 2 (like 2, 4, 8, …, 1024,.., 2 m ) Each word is n-bit wide An m-bit address specifies which word is to be written or read A read and a write signal control read and write operations Some memories are read only (ROM), they are written once or more times using various mechanisms A read/write memory using any address is called RAM Memory unit Data in Read Write RAM Addr Data out

5. 5 There are more than one source of data on a set of wire (bus) We have enable signals to decide who will write on bus The data from bus can be written into more than one units Data are n-bit wide, n depends on data bus width The value of k depends on number of sources Only one source should be enabled on bus We need multiplexing, typically achieved by tri-state buffers An example bus is shown below A bus structure review eke1e0

6. 6 Using the data path design, we can carry out meaningful ops Add two registers and write results in any register Transfer memory data into registers, output Transfer register data into memory, output Now we are ready to write control Mem Unit WM EM Addr RM WAD ALUALU OpCode Reg File WA WR RA2RA1 Input EI Output WOUT EALU M- Reg EMR LDM SHIFTSHIFT SC