2. Princess Sumaya Univ. Computer Engineering Dept. Chapter 4: IT Students

3. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 1 / 52 Stored Program Architecture  Instruction Cycle ●Fetch an instruction from memory ●Decode the instruction ●Get the operands ●Execute the instruction  Where is the next instruction? Program Counter (PC) Instruction Pointer (IP)  Where is the operand? Instructions (Program) Operands (Data) Opcode Operands Binary Operand IT Students

4. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 2 / 52 CPU  Datapath  Control Unit Register File CU ALU IT Students

5. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 3 / 52 General-Purpose Register Organization R1 R2 R3 R4 R5 R6 R7 MUX ALU 3 x 8 Decoder D SEL A SEL B SEL OPR AB IT Students

6. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 4 / 52 General-Purpose Register Organization R1 R2 R3 R4 R5 R6 R7 MUX ALU 3 x 8 Decoder D SEL A SEL B SEL OPR AB Examples: OperationOPRA SEL B SEL D SEL R1 ← R2 − R3 R4 ← SHL R4 IT Students

7. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 5 / 52 General-Purpose Register Organization Examples: OperationOPRA SEL B SEL D SEL R1 ← R2 − R300101010011001 R4 ← SHL R411000100000100 Instructions (Program) Operands (Data) 00101 010 011 001 00 0000 0000 IT Students

8. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 6 / 52 Memory Interface  Address / Data Buses  Read / Write Control  Bidirectional / Unidirectional Data Bus Read Write IT Students

9. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 7 / 52 Building a Datapath  Datapath Elements PC InstructionMemory Addr Data ALU Sel A Sel B Sel C LD Data A Data B Register File Data C Write a program & compile it. Where do you want to put it? Where is the first instruction? What comes out of memory? Where to perform operation? Where are the operands? Who well tell us which reg? Where to store result? Can we save this reg to mem? 32 IT Students

10. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 8 / 52 Building a Datapath  Datapath Elements PC InstructionMemory Addr Data ALU DataMemory Addr Data IT Students Sel A Sel B Sel C LD Data A Data B Register File Data C

11. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 9 / 52 Building a Datapath PC InstructionMemory Addr Data ALU DataMemory Addr Data How can we read it back? IT Students Sel A Sel B Sel C LD Data A Data B Register File Data C

12. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 10 / 52 Building a Datapath PC InstructionMemory Addr Data ALU DataMemory Addr Data Finished executing instruction. Where is the next instruction? Why +4? MUX 4 Adder IT Students Sel A Sel B Sel C LD Data A Data B Register File Data C

13. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 11 / 52 Building a Datapath PC InstructionMemory Addr Data ALU 4 Adder How can we add “immediate”? What if it is negative? SignExtend IT Students Sel A Sel B Sel C LD Data A Data B Register File Data C DataMemory Addr Data MUX

14. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 12 / 52 Building a Datapath PC InstructionMemory Addr Data ALU 4 Adder SignExtend MUX What about “JMP Rel Disp”? It can be positive or negative! IT Students Sel A Sel B Sel C LD Data A Data B Register File Data C DataMemory Addr Data MUX

15. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 13 / 52 Building a Datapath PC 4 Addr Data SignExtend MUX InstructionMemory Shift Left 2 Adder Adder ALU IT Students Sel A Sel B Sel C LD Data A Data B Register File Data C DataMemory Addr Data MUX

16. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 14 / 52 Building a Datapath PC 4 Addr Data SignExtend MUX InstructionMemory Shift Left 2 MUX Adder Adder ALU Why the shift? IT Students Sel A Sel B Sel C LD Data A Data B Register File Data C DataMemory Addr Data MUX

17. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 15 / 52 Building a Datapath PC 4 Addr Data SignExtend MUX InstructionMemory Shift Left 2 MUX Adder Adder ALU Why not use ALU instead of another adder? IT Students Sel A Sel B Sel C LD Data A Data B Register File Data C DataMemory Addr Data MUX

18. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 16 / 52 Cy, Z, etc Adding Control Signals to the Datapath PC 4 Addr Data SignExtend 0 00MUXMUX1100MUXMUX111 InstructionMemory Shift Left 2 0 00MUXMUX1100MUXMUX111 Adder Adder ALU Control Unit Opcode etc IT Students Sel A Sel B Sel C LD Data A Data B Register File Data C DataMemory Addr Data MUX

19. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 17 / 52 Adding Control Signals to the Datapath PC 4 Addr Data SignExtend 0 00MUXMUX1100MUXMUX111 InstructionMemory Shift Left 2 0 00MUXMUX1100MUXMUX111 Adder Adder ALU Control Unit IT Students Sel A Sel B Sel C LD Data A Data B Register File Data C DataMemory Addr Data MUX

20. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 18 / 52 A Simple Implementation Scheme  ALU Control ALU 32 4 ALU Cntrl Cy Z slt R1, R2, R3 Cy = 1  Carry from last adder Z = 1  The result = 0 IT Students

21. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 19 / 52 A Simple Implementation Scheme  Instruction Format ●Arithmetic/Logic OpcodeOperand(s), Address, Code 0 6 RsRs 55556 RtRt RdRd ShiftFunct R d = R s Funct R t FunctALU OperationALU Cntrl Lines 100000Add0010 100010Subtract0110 100100AND0000 100101OR0001 101010SLT0111 Example: 00000000011001110010100000100000 IT Students Sel A Sel B Sel C LD Data A Data B Register File Data C

22. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 20 / 52 A Simple Implementation Scheme  Instruction Format ●Move Immediate OpcodeOperand(s), Address, Code R t = Value Example: R 1 = 12 00110100000000010000 0000 0000 1100 13 6 0 5516 RtRt Immediate IT Students 16 bits (can be positive or negative)

23. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 21 / 52 A Simple Implementation Scheme  Instruction Format ●Load Memory OpcodeOperand(s), Address, Code 35 6 RsRs 5516 RtRt Address R t = M [R s + Addr] 32 bits16 bits (can be positive or negative) Example: R 6 = M [R 4 – 1 ] 10001100100001101111 1111 IT Students

24. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 22 / 52 A Simple Implementation Scheme  Instruction Format ●Store Memory OpcodeOperand(s), Address, Code 43 6 RsRs 5516 RtRt Address M [R s + Addr] = R t Example: M [R 7 – 2 ] = R 9 10101100111010011111 1111 1111 1110 IT Students

25. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 23 / 52 A Simple Implementation Scheme  Instruction Format ●JE Operation OpcodeOperand(s), Address, Code 4 6 RsRs 5516 RtRt Offset If R s = R t then PC = PC + 4*Addr Example: 00010000001001001111 1111 PC is already incremented IT Students

26. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 24 / 52 MUXMUXMUXMUX Final Datapath Design PC 4 Addr Data SignExtend 0 00MUXMUX1100MUXMUX111 InstructionMemory Shift Left 2 0 00MUXMUX1100MUXMUX111 Adder Adder ALU RsRs RtRt Offset, Addr, Immediate RtRt RdRd IT Students Sel A Sel B Sel C LD Data A Data B Register File Data C DataMemory Addr Data MUX

27. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 25 / 52 Program Setup  Write a Program  Assemble it  Store it in Memory Example: 00110100000000010000 0000 0000 101000000000001 00000100000 3 4 0 1 0 0 0 A 0 0 2 1 0 8 2 0 048048 00010000001 1111 1111 1 0 2 1 F F F F IT Students

28. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 26 / 52 Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands  Execute it CLK PC I-Mem 0 ƮMƮM 3401000A (MOV R 1, 10) 130110 RsRs RtRt Immediate Reg A Sel 00 Data A Ʈ Reg 1 Reg C Sel Reg C LD ALU MUX 2 (Add) ALU Ctrl Mem MUX 10 Sign Ext 10 ALU Ʈ ALU 10 Data C Adder MUX 4 PC Adder Ʈ Adder Ʈ Reg IT Students

29. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 27 / 52 Datapath Operation  How Fast Can the Clock Be? CLK PC I-Mem 0 ƮMƮM 3401000A (MOV R 1, 10) Reg A Sel 00 Data A Ʈ Reg 1 Reg C Sel Reg C LD ALU MUX 2 (Add) ALU Ctrl Mem MUX 10 Sign Ext 10 ALU Ʈ ALU 10 Data C Adder MUX 4 PC Adder Ʈ clk Ʈ Reg IT Students

30. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 28 / 52 Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands  Execute it CLK PC I-Mem 4 00210820(Add R 1,R 1,R 1 ) Reg A Sel 110 Data A 1 Reg C Sel Reg C LD ALU MUX 2 (Add) ALU Ctrl Mem MUX 10 Data B 20 ALU 20 Data C Adder MUX 8 PC Adder 01132 RsRs RtRt FunctRdRd 10 Shift 0 4 0 1 2 0 10 IT Students

31. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 29 / 52 Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands  Execute it CLK PC I-Mem 8 1021FFFF (JE R 1,R 1,-1) Reg A Sel 120 Data A 1 Reg C Sel Reg C LD ALU MUX 6 (Sub) ALU Ctrl 20 Data B 0 ALU 12 PC Adder 411– 1 RsRs RtRt Offset 4 8 1 1 2 10 20 10 PC Adder 2 8 Adder MUX IT Students

32. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 30 / 52 Datapath Operation  How Fast Can the Clock Be? CLK PC I-Mem 8 1021FFFF (JE R 1,R 1,-1) Reg A Sel 120 Data A 1 Reg C Sel Reg C LD ALU MUX 6 (Sub) ALU Ctrl 20 Data B 0 ALU 12 PC Adder 4 8 1 1 2 10 20 10 PC Adder 2 8 Adder MUX ƮMƮM Ʈ Reg Ʈ ALU IT Students

33. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 31 / 52 Datapath Operation  How Fast Can the Clock Be? CLK PC I-Mem 8 1021FFFF (JE R 1,R 1,-1) Reg A Sel 120 Data A 1 Reg C Sel Reg C LD ALU MUX 6 (Sub) ALU Ctrl 20 Data B 0 ALU 12 PC Adder 4 8 1 1 2 10 20 10 PC Adder 2 8 Adder MUX Ʈ Adder Ʈ clk Ʈ Reg Ʈ ALU ƮMƮM IT Students

34. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 32 / 52 Single-Cycle Implementation  Fetch Instruction  Decode Instruction  Get Operands  Execute it CLK PC I-Mem i 8C640007 (LD R 4,[R 3 +7]) 35347 RsRs RtRt Address Reg A Sel 3 d Data A 4 Reg C Sel Reg C LD ALU MUX 2 (Add) ALU Ctrl Mem MUX 7 Sign Ext d +7 ALU v Data C D-Mem v IT Students

35. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 33 / 52 Single-Cycle Implementation  Clock Speed? CLK PC I-Mem i 8C640007 (LD R 4,[R 3 +7]) Reg A Sel 3 d Data A 4 Reg C Sel Reg C LD ALU MUX 2 (Add) ALU Ctrl Mem MUX 7 Sign Ext d +7 ALU v Data C D-Mem v ƮMƮM Ʈ Reg Ʈ ALU Ʈ clk Ʈ Reg ƮMƮM IT Students

36. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 34 / 52 Single-Cycle Implementation Example: Ʈ M = 200 picoseconds Ʈ ALU = 100 picoseconds Ʈ Adder = 100 picoseconds Ʈ Reg = 50 picoseconds Fastest Clock? MOV/ALU: Ʈ clk > Ʈ M + 2 Ʈ Reg + Ʈ ALU Conditional Jump: Ʈ clk > Max Ʈ M + Ʈ Reg + Ʈ ALU Load Memory: Ʈ clk > 2 Ʈ M + 2 Ʈ Reg + Ʈ ALU Store Memory: Ʈ clk > 2 Ʈ M + Ʈ Reg + Ʈ ALU TypeDelay MOV / ALU400 ps LD600 ps ST550 ps Cond. Jump350 ps Ʈ clk = ps  GHz IT Students Max + Ʈ Adder Ʈ M Ʈ Adder

37. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 35 / 52 Multicycle Implementation  Instructions take different number of clock cycles  Functional units can be shared within the execution of a single instruction IT Students IR MDR X Y Result ALU Memory Addr Data PC Sel A Sel B Sel C LD Data A Data B Register File Data C

38. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 36 / 52 Multicycle Implementation  Some registers are not visible to the programmer IR MDR X Y Result ALU Memory Addr Data PC 4 SignExtend Shift Left 2 Exercise: Can you do all the previous instruction here? IT Students Sel A Sel B Sel C LD Data A Data B Register File Data C

39. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 37 / 52 Multicycle Implementation  Some registers are not visible to the programmer IR MDR X Y Result ALU Addr Data PC 4 SignExtend Shift Left 2 01 0123 01 01 01 Memory 01 IT Students Sel A Sel B Sel C LD Data A Data B Register File Data C

40. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 38 / 52 Multicycle Datapath Operation  Fetch Instruction CLK PC 0 ƮMƮM 3401000A Y MUX 2 (Add) ALU Ctrl PC MUX X MUX 4 ALU Ʈ ALU 0 IR LD Mem Rd PC LD Ʈ clk 1 IR Mem Out IT Students

41. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 39 / 52 Multicycle Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands CLK PC 4 0 2 3401000A (MOV R 1, 10) 130110 RsRs RtRt Immediate Reg A Sel 0 X LD 0 Data A Ʈ Reg X 10 Sign Ext Ʈ clk IR LD Mem Rd IR Mem Out IT Students

42. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 40 / 52 Multicycle Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands  Execute it CLK PC 4 IR 3401000A (MOV R 1, 10) 130110 RsRs RtRt Immediate 3 X 0 Y MUX ALU Ctrl X MUX ALU 2 2 (Add) 10 Ʈ ALU Result LD Result Ʈ clk X LD IT Students

43. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 41 / 52 Multicycle Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands  Execute it CLK PC 4 IR 3401000A (MOV R 1, 10) 130110 RsRs RtRt Immediate 4 Result LD Result Ʈ clk 10 C MUX Reg C LD Ʈ Reg Ʈ clk Reg C Sel 1 IT Students

44. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 42 / 52 Multicycle Implementation Example: Ʈ M = 200 picoseconds Ʈ ALU = 100 picoseconds Ʈ Adder = 100 picoseconds Ʈ Reg = 50 picoseconds Fastest Clock? Load Immediate/ALU: 4 Clocks Load Memory: 5 Clocks Store Memory: 4 Clocks TypeInstr. Mix LI / ALU52% LD25% ST10% Cond. Jump13% Ʈ clk = ps  GHz Conditional Jump: 3 Clocks IT Students

45. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 43 / 52 Control Implementation Control Unit CU Data Processing Unit DPU or Datapath Datapath Control Signals: ALU Operation, MUX Selection, Memory Rd/Wr, etc Datapath Control Signals: ALU Operation, MUX Selection, Memory Rd/Wr, etc Datapath Status Signals: IR Fields, ALU Flags Datapath Status Signals: IR Fields, ALU Flags IT Students

46. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 44 / 52 Control Implementation  Hardwired ●Standard Logic Components ●Fast ●Not Flexible, i.e. Difficult to Change Control Operation  Microprogrammed ●Memory-Based ●Speed Function of Memory (slower than hardwired) ●Flexible Design IT Students

47. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 45 / 52 Control Implementation  Hardwired ●Finite State Machine State Register Combinational Control Logic Datapath Control Outputs Datapath Control inputs IT Students

48. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 46 / 52 Microprogrammed Control Implementation  Each Line in the Micro- Program Executes Micro- Operations (in 1 Clock)  Fetch, Decode, Execute Cycle ALU Operation, MUX Selection, Memory Rd/Wr, etc IT Students

49. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 47 / 52 Microprogram Control Unit Datapath Control Signals: IT Students

50. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 48 / 52 Microprogram Control Unit C 19 C 0 1 Opcode Funct Z Cy etc Adder IT Students

51. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 49 / 52 0 1 Microprogram Control Unit  Fetch Instruction μPC M 0 S 1 S 0 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 IR  M[PC] PC  PC + 4 IT Students

52. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 50 / 52 Microprogram Control Unit  Decode / Get Operands 0 1 1 1 0 1 0 0 0 0 0 1 0 IR  M[PC] PC  PC + 4 0 0 0 0 0 1 0 0 1 X  Reg[IR[25:21]] Y  Reg[IR[20:16]] Opcode = 0 Funct = 100010 = 8 IT Students 0 1 8 μPC M 0 S 1 S 0 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0

53. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 51 / 52 Microprogram Control Unit  Execute Instruction IR  M[PC] PC  PC + 4 X  Reg[IR[25:21]] Y  Reg[IR[20:16]] 1 0 0 R  X – Y Opcode = 0 Funct = 100010 = 8 IT Students 0 1 8 9 μPC M 0 S 1 S 0 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 1 1 0 1 1 1 0 1 0 0 0 0 0 1 00 0 0 0 0 1 0 0 1

54. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. 52 / 52 Microprogram Control Unit  Execute Instruction IR  M[PC] PC  PC + 4 X  Reg[IR[25:21]] Y  Reg[IR[20:16]] R  X – Y 1 0 1 0 1 1 0 1 0 0 1 0 0 1 0 0 1 Reg[IR[15,11]]  R Opcode = 0 Funct = 100010 = 8 IT Students 0 1 8 9 μPC M 0 S 1 S 0 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 1 0 0 1 1 0 1 1 1 0 1 0 0 0 0 0 1 00 0 0 0 0 1 0 0 1

55. Princess Sumaya University 22342 – Computer Org. & Assembly Lang. Computer Engineering Dept. Chapter 4