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Memory & IO Interfacing to CPU
Lec note 3
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outline Z80 Minimal Configuration Z80 Memory connection
Address Bit Map Memory Map Full and Partial Decoding 1 Bit Memory With Separated I/O Z80 Input Output Simplified Drawing of 8088 Minimum Mode 8088 Memory connection
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Minimal Configuration of a Z80 Microcomputer
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Z80 Memory connection CPU 16 bit address bus 64 k memory(max)
CPU 8 bit data bus 8 bit data width Generally should be connected Data to data Address to address Wr to wr Rd to rd Mreq to cs
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Memory connection (cont.)
If only one RAM chip Full size (64 kb capacity) RAM 64 kb Z80 CPU D7~D0 A15~A0
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Memory connection (cont.)
If RAM capacity was 32 kb A15 composed with MREQ RAM area is from 0000h to 7FFFh RAM 32 kb Z80 CPU D7~D0 A14~A0 A15
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Memory connection (cont.)
There is two 32 kb RAM Problem: Bus Conflict. The two memory chips will provide data at the same time when microprocessor performs a memory read. Solution: Use address line A15 as an “arbiter”. If A15 outputs a logic “1” the upper memory is enabled (and the lower memory is disabled) and vice-versa.
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Memory connection (cont.)
There is two 32 kb RAM A15 applied to select one RAM chip Two RAM area is from 0000h to 7FFFh (RAM1) and 8000h to FFFFh (RAM1) RAM 32 kb Z80 CPU D7~D0 A14~A0 A15
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Memory connection (cont.)
32 kb ROM and 32 kb RAM ROM doesn’t have wr signal ROM 32 kb Z80 CPU D7~D0 A14~A0 RAM A15
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Memory connection (cont.)
There is 4 memory chip A14 and A15 applied to chip selection ROM 16 kb D7~D0 A13~A0 RAM A15 A14 En S0 S1 Z80 CPU
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Address Bit Map Selects chip Selects location within chips A15 to A0
(HEX) AA AA 11 11 54 32 AAAA 1198 10 7654 3210 Memory Chip 0000h 3FFFh 00 00 00 11 0000 1111 ROM 4000h 7FFFh 01 00 01 11 RAM1 8000h BFFFh 10 00 10 11 RAM2 C000h FFFFh 11 00 RAM3
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Memory Map ROM Represents the memory type RAM1
Address area of each memory chip Empty area 0000h 3FFFh ROM 16k 4000h 7FFFh RAM1 8000h BFFFh RAM2 C000h FFFFh RAM3 ROM 16 kb D7~D0 A13~A0 RAM A15 A14 En S0 S1
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Memory Map ROM RAM2 RAM3 0000h 3FFFh 4000h
Empty Area cann’t write and read Read op. returns FFh value (usualy) Write op. cann’t store any value on it 0000h 3FFFh ROM 4000h 7FFFh Empty 8000h BFFFh RAM2 C000h FFFFh RAM3 ROM 16 kb D7~D0 A13~A0 A15 RAM A14 En S0 S1
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Memory Map ROM RAM 0000h 3FFFh 4000h Empty Area cann’t write and read
Read op. returns FFh value (usualy) Write op. cann’t store any value on it 0000h 3FFFh ROM 4000h 7FFFh Empty 8000h BFFFh RAM C000h FFFFh ROM 16 kb D7~D0 A13~A0 A15 RAM A14 En S0 S1
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Full and Partial Decoding
Full (exhaust) Decoding All of the address lines are connected to any memory/device to perform selection Absolute address : any memory location has one address Partial Decoding When some of the address lines are connected the memory/device to perform selection Using this type of decoding results into roll-over addresses (fold back or shading). roll-over address : any memory location has more than one address
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Partial Decoding A15~A12 has no connection
Then doesn’t play any role in addressing What is the Memory and Address Bit map? RAM 4 kb Z80 CPU D7~D0 A11~A0 X A15~A12
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Partial Decoding Roll-over Address
0000h 0FFFh RAM 1000h 1FFFh RAM’ 2000h 2FFFh 3000h 3FFFh F000h FFFFh Every memory location has more than one address For example first RAM location has addresses: 0000h 1000h 2000h 3000h ……………. F000h Roll-over Address RAM 4 kb Z80 CPU D7~D0 A11~A0 X A15~A12 A15 to A0 (HEX) AAAA 1111 5432 1198 10 7654 3210 Memory Chip X000h XFFFh xxxx 0000 RAM
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Partial Decoding X Z80 CPU A12 only connected to RAM
A13 has no connection What is the memory map? D7~D0 D7~D0 D7~D0 ROM 4 kb RAM 8 kb A12~A0 A11~A0 A12~A0 A13 X Z80 CPU A14 A15
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Partial Decoding 8 roll-over address for ROM
4 roll-over address for RAM ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb A14 A15 X A13 AAAA 1111 5432 1198 10 7654 3210 Memory Chip 0xxx 0000 ROM X0x0 X0x1 RAM
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Partial Decoding Conflict X RAM’ ROM ROM’ RAM Z80 CPU AAAA 1111 5432
0000h 1FFFh RAM’ 0FFFh ROM 1000h ROM’ 2000h 3FFFh 2FFFh 3000h 4000h 5FFFh 4FFFh 5000h 6000h 7FFFh 6FFFh 7000h 8000h 9FFFh RAM F000h FFFFh A000h BFFFh C000h DFFFh E000h Conflict ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb A14 A15 X A13 AAAA 1111 5432 1198 10 7654 3210 Memory Chip 0xxx 0000 4k ROM X0x0 X0x1 8k RAM
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Partial Decoding Conflict X ROM ROM’ RAM’ RAM Z80 CPU AAAA 1111 5432
0000h 1FFFh 0FFFh ROM 1000h ROM’ 2000h 3FFFh 2FFFh 3000h 4000h 5FFFh RAM’ 4FFFh 5000h 6000h 7FFFh 6FFFh 7000h 8000h 9FFFh F000h FFFFh A000h BFFFh C000h DFFFh RAM E000h Partial Decoding ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb A14 A15 X A13 Conflict AAAA 1111 5432 1198 10 7654 3210 Memory Chip 0xxx 0000 4k ROM X1x0 X1x1 8k RAM
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Full (exhaustive) decoding
AAAA 1111 5432 1198 10 7654 3210 Memory Chip 0000 0001 ROM 0010 0111 RAM A12~A0 A12~A0 D7~D0 2764 EPROM 8k8 D7~D0 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 A13 0000h-07FFh A12 0800h-0FFFh A11 7421 1000h-17FFh A10~A0 A10~A0 1800h-1FFFh D7~D0 2000h-27FFh 6116 RWM 2k8 A15 A14
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Partial decoding 74138 A12~A0 A12~A0 D7~D0 D7~D0 Y0 Y1 Y2 Y3 Y6 Y4 Y7
1111 5432 1198 10 7654 3210 Memory Chip 0000 0001 ROM 001x x000 x111 RAM A12~A0 A12~A0 D7~D0 2764 EPROM 8k8 D7~D0 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 A15 0000h-1FFFh A14 2000h-3FFFh A13 A10~A0 A10~A0 D7~D0 6116 RWM 2k8 GND VCC
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1 Bit Memory With Separated I/O
D7-D0 D7 D1 D0 Din Din Din A11~A0 Dout A11~A0 Dout A11~A0 Dout A11-A0 A11-A0 A11-A0 2147 RWM 4k1 2147 RWM 4k1 2147 RWM 4k1
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What is the memory(addr. bit) map
A12~A0 D7~D0 2764 EPROM 8k8 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 A15 0000h-1FFFh A14 2000h-3FFFh D7-D0 D7 D1 D0 A13 Din Din Din A11~A0 Dout A11~A0 Dout A11~A0 Dout A11-A0 A11-A0 A11-A0 2147 RWM 4k1 2147 RWM 4k1 2147 RWM 4k1 GND VCC
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Adding RAM & ROM
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Minimum Z80 Computer System
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Z80-µP-Family (Typical Environment)
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Z80 Input Output Z80 at most could have 256 input port and 256 output
8 bit port address is placed on A7–A0 pin to select the I/O device OUT (n), A n is 8 bit port address Content of A is data OUT (C), r Content of C is a port address r is a data register IN A, (n) Data is transfered to A IN r (C) Content of Reg C is a port address Input data is transfered to r (data reg)
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Remember IO read/write cycle
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Z80 and simple output port
OUT (03), A Z80 CPU A14 A0 : D7 D6 WR IORQ A15 D5 D4 D3 D2 D1 D0 A 7 6 5 4 3 2 1 IOWR 74LS373 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OE LE
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Z80 and simple input port IN A, (02) Z80 CPU 74LS244 A15 A14 : A0 D7
5V A14 : A0 D7 Y0 A0 D6 Y1 A1 D5 Y2 A2 Z80 CPU D4 Y3 A3 D3 Y4 74LS244 A4 D2 Y5 A5 D1 Y6 A6 D0 Y7 A7 G1 G2 IORQ RD A A A A A A A A IORD 7 6 5 4 3 2 1
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8088 and simple output port 8088 Minimum Mode 74LS373 A 1 5 A18 A0 :
IOR IOW A19 D5 D4 D3 D2 D1 D0 4 3 2 9 8 7 6 74LS373 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OE LE
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8088 and simple input port What is this? 8088 Minimum Mode 74LS244 A 1
5 8088 Minimum Mode A18 A0 : D7 D6 IOR IOW A19 D5 D4 D3 D2 D1 D0 4 3 2 9 8 7 6 What is this? 74LS244 A1 A2 A3 A4 A5 A6 A7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 G1 G2 5V
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Simplified Drawing of 8088 Minimum Mode
Q7 - Q0 OE LE 74LS373 8088 AD7 - AD0 A15 - A8 A19/S6-A16/S3 DEN DT/R IO / M RD WR ALE D7 - D4 Q7 - Q4 D3 - D0 Q3 - Q0 GND A7 - A0 B7 - B0 E DIR 74LS245 MEMR MEMW IOR IOW A7-A0 A15-A8 A19-A16 D7-D0
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Minimum Mode 220 bytes or 1MB memory Simplified Drawing of 1 MB
A19 - A0 RD WR Simplified Drawing of 8088 Minimum Mode MEMR MEMW CS
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Memory location What is the memory location of a 1MB (220 bytes) Memory? A19 to A0 (HEX) AAAA 1111 9876 5432 1198 10 7654 3210 00000 0000 FFFFF Example: 34FD0
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Minimum Mode 512 kB memory What do we do with A19? Don’t connect it
D7 - D0 D7 - D0 What do we do with A19? Don’t connect it Connect to cs What is the difference? A19 A18 - A0 A18 - A0 Simplified Drawing of 512 kB Memory 8088 Minimum Mode MEMR RD MEMW WR CS
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512 kB Memory Map Don’t connect it Connect to cs
A19 is not connected to the memory so even if the 8088 microprocessor outputs a logic “1”,the memory cannot “see” it. A19=0 is the same as A19=1 for Memory Connect to cs If A19=0 Memory chip act normal fanction 00000h 7FFFFh 512k Mem 80000h FFFFFh Mem’ 00000h 7FFFFh 512k Mem 80000h FFFFFh Empty
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2 512 kB memory 512 kB RAM1 Simplified Drawing of 8088 Minimum Mode
A18 - A0 A18 - A0 MEMR RD MEMW WR CS Simplified Drawing of 8088 Minimum D7 - D0 Mode 512 kB RAM2 A18 - A0 MEMR RD MEMW WR CS
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2512 kB memory What are the memory locations of two consecutive 512KB (219 bytes) Memory? 00000h 7FFFFh 512k RAM1 80000h FFFFFh RAM2 AAAA 1111 9876 5432 1198 10 7654 3210 Memory Chip 0000 0111 ROM 1000 RAM
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Interfacing four 256K Memory Chips to 8088 Microprocessor
Minimum Mode A17 A0 : D7 D0 MEMR MEMW A18 256KB #3 RD WR CS A19 #2 #1 #4
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Interfacing four 256K Memory Chips to 8088 Microprocessor
Minimum Mode A17 A0 : D7 D0 MEMR MEMW A18 256KB #3 RD WR CS A19 #2 #1 #4
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Memory chip#__ is mapped to:
AAAA 1111 9876 5432 1198 10 7654 3210 Memory Chip RAM#1 RAM#2 RAM#3 RAM#4
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Interfacing several 8K Memory Chips to 8088 P
Minimum Mode A12 A0 : D7 D0 MEMR MEMW A13 A14 8KB #2 RD WR CS #1 #? A15 A16 A17 A18 A19
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Interfacing 128 8K Memory Chips to 8088 P
Minimum Mode A12 A0 : D7 D0 MEMR MEMW A13 A14 8KB #2 RD WR CS #1 #128 A15 A16 A17 A18 A19
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Interfacing 128 8K Memory Chips to 8088 P
Minimum Mode A12 A0 : D7 D0 MEMR MEMW A13 A14 8KB #2 RD WR CS #1 #128 A15 A16 A17 A18 A19
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Memory chip#__ is mapped to:
AAAA 1111 9876 5432 1198 10 7654 3210 Memory Chip RAM#1 RAM#2 RAM#126 RAM#127 RAM#128
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Memory map & Address Bit map
A12~A0 A12~A0 D7~D0 2764 EPROM 8k8 D7~D0 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 7408 A14 A13 A12 A10~A0 A10~A0 D7~D0 74244 6116 RWM 2k8 input A15 VCC
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8255 Programmable Peripheral Interface (PPI)
Has 3 8_bit ports A, B and C Port C can be used as two 4 bit ports CL and Ch Two address lines A0, A1 and a Chip select CS 8255 can be configured by writing a control-word in CR register
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Interfacing with 8255 8255 74138 /CS A0 A1 D7-D0 A2 C Y0 A3 B Y1 A4 A
G2A G2B G1 A2 A3 /CS A4 8255 A0 A0 A1 A1 A5 A6 D7-D0 D7-D0 /WR /RD /WR /RD
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