Dept. of Electrical and Computer Eng., NCTU 1 Lab 8. D-type Flip-Flop Presenter: Chun-Hsien Ko Contributors: Chung-Ting Jiang and Lin-Kai Chiu

Logic DesignLab 8. D-type Flip-FlopChun-Hsien Ko Dept. of Electrical and Computer Eng., NCTU 2 Sequential Logic Circuits Status (Memory) and Timing (Clock) How to Save the Status? Latch, e.g., SR Latch Flip-Flop, e.g., D-FF (D-type Flip-Flop) LAB: IC ： 7400 (NAND) x 2 、 LED x 1

Logic DesignLab 8. D-type Flip-FlopChun-Hsien Ko Two Types of Logic Circuits Combinational logic circuits depends only on current inputs E.g., A + B = C Sequential logic circuits depends on past and current inputs E.g., A[n]=A[n-1]+B Dept. of Electrical and Computer Eng., NCTU 3 Memory and Clock!!

Logic DesignLab 8. D-type Flip-FlopChun-Hsien Ko SR Latch Steady state results Feedback from output Dept. of Electrical and Computer Eng., NCTU 4 R S Q Q’ InputFunction S = 1 ， R = 0 Set ( Q = 1 ) S = 0 ， R = 1 Reset ( Q = 0 ) S = 1 ， R = 1 Hold ( Q = Q ) S = 0 ， R = 0 Not Allow R S Q Q’ R S Q R S Q 1 1 Q

Logic DesignLab 8. D-type Flip-FlopChun-Hsien Ko SR Latch Steady state results Feedback from output Dept. of Electrical and Computer Eng., NCTU 5 (1) (2) 1 (3) R S Q Q’ InputFunction S = 1 ， R = 0 Set ( Q = 1 ) S = 0 ， R = 1 Reset ( Q = 0 ) S = 1 ， R = 1 Hold ( Q = Q ) S = 0 ， R = 0 Not Allow R S Q Q’ R S Q R S Q 1 1 Q 1 (4) 0 (1) (2) 1 (3) 1 (4) 0 (1) 0/1 (2) 0/1 (3) 1/0 (4) 1/0 A NAND 1 = A’

Logic DesignLab 8. D-type Flip-FlopChun-Hsien Ko Timing: Clock Input When to set and reset How to synchronize devices with memory Positive (rising) edge triggered Negative (falling) edge triggered Dept. of Electrical and Computer Eng., NCTU 6 time

Logic DesignLab 8. D-type Flip-FlopChun-Hsien Ko Flip Flops Using clock input to determine the status changing Different types of Flip-Flop SR (Set and Reset) D (Input = Output), T (Input != Output) JK (When S=0, R=0, Q=Q’) Trigger type Rising(positive)-edge Falling(negative)-edge Dept. of Electrical and Computer Eng., NCTU 7

Logic DesignLab 8. D-type Flip-FlopChun-Hsien Ko LAB 8: Implement a D-FF with NAND gates Goal: D-type positive edge triggered Flip-Flop IC ： 7400 (NAND) x 2 、 LED x 1 Dept. of Electrical and Computer Eng., NCTU 8 CLKInputStateOutput 0->0DSS 0->1DSD 1->1DSS 1->0DSS

Logic DesignLab 8. D-type Flip-FlopChun-Hsien Ko CLK: 0->1, S = D, R = D’; otherwise, R=1, S=1 Dept. of Electrical and Computer Eng., NCTU R S D Clock Q Q’ SR Latch

Logic DesignLab 8. D-type Flip-FlopChun-Hsien Ko Dept. of Electrical and Computer Eng., NCTU 10 R S D Clock Clock = 1, D: X->X’ R S D Clock Clock: 0->1 R S D Clock Clock = X’ X 0->1 1->X’ 1->X X’ X X 1 X X’->1 X->X X X->X’ S, R = 1  Hold S = X, R = X’  Set the latch as X S, R will not change with D

Logic DesignLab 8. D-type Flip-FlopChun-Hsien Ko How to implement 3-input NAND gate? Dept. of Electrical and Computer Eng., NCTU R S D Clock Q Q’ How to realize 3-inputs NANDs with 2-inputs NANDs? 3

Logic DesignLab 8. D-type Flip-FlopChun-Hsien Ko You can connect output of 555 to a buffer Oscillator would be more stable E.g., connect output of 555 to an inverter or AND output of 555 with signal 1 Dept. of Electrical and Computer Eng., NCTU Calculator (Website) + -