1. Yee-Wing Hsieh Steve Jacobs
Lab7: Sequential Logic
Yee-Wing Hsieh
Steve Jacobs

2. Outline Logic Duals Memory Crossed Coupled RS Latch D-Latch
Master-Slave D Flip-Flop

3. Demorgan’s Theorem and Logic Duals
NAND Gate
Truth Table for NAND Gate?
NOR Gate
Truth Table for NOR Gate?

4. Demorgan’s Theorem and Logic Duals
NAND Gate
Truth Table for NAND Gate
NOR Gate
Truth Table for NOR Gate

5. Demorgan’s Theorem and Logic Duals
NAND Gate
Truth Table for NAND Gate
NOR Gate
Truth Table for NOR Gate

6. Demorgan’s Theorem and Logic Duals
NAND Gate
Truth Table for NAND Gate
NOR Gate
Truth Table for NOR Gate

7. Demorgan’s Theorem and Logic Duals
NAND Gate
Truth Table for NAND Gate
NOR Gate
Truth Table for NOR Gate

8. Memory, Time and Propagation Delay
Why do we need memory?
store and retrieve data to perform computation
What are the specifications?
store data in a device (i.e., store ‘1’ and ‘0’ => set and reset)
retain data in a device (i.e., hold data in a device regardless of input changes)
How does it work?
propagation delay => time
feedback => past history

9. Memory, Time and Propagation Delay
Why do we need memory?
store and retrieve data to perform computation
What are the specifications?
store data in a device (i.e., store ‘1’ and ‘0’ => set and reset)
retain data in a device (i.e., hold data in a device regardless of input changes)
How does it work?
propagation delay => time
feedback => past history

10. Memory, Time and Propagation Delay
Why do we need memory?
store and retrieve data to perform computation
What are the specifications?
how to store the data (i.e., store ‘1’ and ‘0’ => set and reset)
must retain the data for later use (i.e., hold data in a device regardless of input changes)
How does it work?
propagation delay => time
feedback => past history

11. Memory, Time and Propagation Delay
Why do we need memory?
store and retrieve data to perform computation
What are the specifications?
how to store the data (i.e., store ‘1’ and ‘0’ => set and reset)
must retain the data for later use (i.e., hold data in a device regardless of input changes)
How does it work?
feedback => needed to create sequential logic
propagation delay => time until data is valid

12. Gate Propagation Delay
Three Cascaded Inverters (combinational)
Timing Diagram
Z(t + 3) = W´(t)

13. Feedback Circuits Ring Oscillators (sequential) Timing Diagram
Z(t + 3) = Z´(t)

14. Crossed Coupled RS-Latch
Logic Diagram
Truth Table?
“0” activates ‘set’ or ‘reset’ (active low)
How can we avoid the illegal case?

15. Crossed Coupled RS-Latch
Logic Diagram
Truth Table
“0” activates ‘set’ or ‘reset’ (active low)
How can we avoid the illegal case?

16. D-Latch
Logic Diagram
Truth Table?

17. D-Latch
Logic Diagram
Truth Table
Timing Diagram?

18. D-Latch
Logic Diagram
Timing Diagram (without gate delay)

19. D-Latch Timing Diagram
Without Gate Delay
With Gate Delay

20. Master/Slave Flip Flop
Logic Diagram (two D-Latch with an inverted Clock)
Timing Diagram?

21. Master/Slave Flip Flop
Logic Diagram (two D-Latch with an inverted Clock)
Timing Diagram (without gate delay)

22. Master/Slave Flip Flop (Optimized)
Logic Diagram
This circuit serves as a falling-edge-triggered D flip-flop