1. FLIP-FLOPS

2. Flip Flop (Sequential Circuits)
What is Flip flop?
Answer: In digital circuits, the flip-flop, is a kind of bi-stable multivibrator.
It is a Sequential Circuits / an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory , bit 1 or bit 0.

3. Introduction – Flip Flop
They are 1 (HIGH) or 0 (LOW).
Whenever we refer to the state of flip flop, we refer to the state of its normal output (Q).
More complicated Flip flop complicated Flip flop complicated Flip flop complicated Flip flop use a clock as the control input. These clocked flip-flops are used whenever the input and output signals must occur within a particular sequence.
They have two stable conditions and can be switched from one to the other by appropriate inputs. These stable conditions are usually called the states of the circuit.

4. Introduction: Types Of Flip Flop
1. SR Flip Flop SR Flip Flop SR Flip Flop SR Flip Flop
a.SR Flip Flop Active Low = NAND gates
b. SR Flip Flop Active High = NOR gates
2. Clocked SR Flip Flop
3. JK Flip Flop
4. JK Flip Flop With Pre-set And Clear
5. T Flip Flop
6. D Flip Flop
7. Master-Slave Edge-Triggered Flip-Flop

5. The Used of Flip Flop For Memory circuits For Logic Control Devices
For Counter Devices
For Register Devices

6. SR Flip Flop
The most basic Flip Flop is called SR Flip Flop SR Flip Flop SR Flip Flop SR Flip Flop.
The basic RS flip flop is an asynchronous device.
In asynchronous device, the outputs is immediately changed anytime one or more of the inputs change just as in combinational logic circuits.
It does not operate in step with a clock or timing.
These basic Flip Flop circuit can be constructed using two NAND gates latch or two NOR gates latch.
SR Flip Flop Active Low SR Flip Flop Active Low SR Flip Flop Active Low SR Flip Flop Active Low = NAND gates
SR Flip Flop Active High SR Flip Flop Active High SR Flip Flop Active High SR Flip Flop Active High = NOR gates

7. SR Flip Flop The SR Flip Flop has two inputs, SET (S) and RESET (R).
The SR Flip Flop has two outputs, Q and ¯
The Q output is considered the normal output and is the one most used.
The other output ¯ is simply the compliment of output Q.

8. SR Flip Flop - NAND GATE LATCH
The NAND gate version has two inputs, SET (S) and RESET (R).
Two outputs, Q as normal output and ¯ as inverted output and feedback mechanism.
The feedback mechanism is required to form a sequential circuit by connecting the output of NAND-1 to the input of NAND-2 and vice versa.
The circuit outputs depends on the inputs and also on the outputs.

9. SR Flip Flop - NAND GATE LATCH
From the description of the NAND gate latch operation, it shows that the SET and RESET inputs are active LOW.
The SET input will set Q = 1 when SET is 0 (LOW).RESET input will reset Q = 0 when RESET is 0 (LOW)
In the prohibited/INVALID state both outputs are 1. This condition is not used on the RS flip-flop. The set condition means setting the output Q to 1.
Likewise, the reset condition means resetting (clearing) the output Q to 0. The last row shows the disabled, or hold , condition of the RS flip-flop. The outputs remain as they were before the hold condition existed. There is no change in the outputs from the previous states

10. SR Flip Flop - NOR GATE LATCH NOR GATE LATCH NOR GATE LATCH NOR GATE LATCH
The latch circuit can also be constructed using two NOR gates latch.
The construction is similar to the NAND latch except that the normal output Q and inverted output ¯ have reversed positions.

11. SR Flip Flop - NOR GATE LATCH
S = 1, R = 0; This will set Q to 1, it works in SET mode operation.
S = 1, R = 1; This condition tries to set and reset the NOR gate latch at the same time, and it produces Q = ¯ = 0 This is an unexpected condition and are not used.
Since the two outputs should be inverse of each other. If the inputs are returned to 1 simultaneously, the output states are unpredictable.
This input condition should not be used and when circuits are constructed, the design should make this condition SET=RESET = 1 never arises

12. SR Flip Flop - NOR GATE LATCH
From the description of the NOR gate latch operation, it shows that the SET and RESET inputs are Active HIGH.
The SET input will set Q = 1 when SET is 1 (HIGH). RESET input will reset Q when RESET is 1 (HIGH).

13. The CLOCK
When the clock changes from a LOW state to a HIGH state, this is called the positive-going transition (PGT) or positive edge triggered.
When the clock changes from a HIGH state to a LOW state, it is called negative going transition (NGT) or negative edge triggered.

14. Clocked SR Flip Flop
Additional clock input is added to change the SR flip- flop from an element used in asynchronous sequential circuits to one, which can be used in synchronous circuits.
The clocked SR flip flop logic symbol that is triggered by the PGT is shown in Figure.
Its means that the flip flop can change the output states only when clock signal makes a transition from LOW to HIGH.

15. Clocked RS Flip Flop
The Truth Table in figure shows how the flip flop output will respond to the PGT at the clocked input for the various combinations of SR inputs and output.
The up arrow symbol indicates PGT.

16. Clocked SR Flip Flop
The clocked SR Flip Flop logic symbol that is triggered by the NGT is shown in Figure.
It means that the Flip flop can change the output states only when clocked signal makes a transition from HIGH to LOW

17. Clocked SR Flip Flop CLOCKED SR FLIP FLOP LOGIC CIRCUIT
If used NOR Gate NOR Gate NOR Gate NOR Gate, must used AND Gate in front.

18. JK Flip Flop - Symbol Another types of Flip flop is JK flip flop.
It differs from the RS flip flops when J=K=1 condition is not indeterminate but it is defined to give a very useful changeover (toggle) action.
Toggle means that Q and ¯ will switch to their opposite states.
The JK Flip flop has clock input Cp and two control inputs J and K.
Operation of Jk Flip Flop is completely described by truth table in Figure.

19. JK Flip Flop – Truth Table And Logic Circuit

20. JK Flip Flop with Asynchronous Input
The J and K inputs are called synchronous inputs since they only influence the state of the flip flop when the clocked pulse is present.
This flip flop can also have other inputs called Pre-set (or SET) and clear that can be used for setting the flip flop to 1 or resetting it to 0 by applying the appropriate signal to the Pre-set and Clear inputs.
These inputs can change the state of the flip flop regardless of synchronous inputs or the clock

21. JK Flip Flop with Preset and Clear

22. JK Flip Flop with Asynchronous Input

23. JK Flip Flop with Asynchronous Input

24. T Flip Flop - Symbol
The T flip flop has only the Toggle and Hold Operation.
If Toggle mode operation. The output will toggle from 1 to 0 or vice versa.

25. T Flip Flop – Logic Circuit
Logic circuit T Flip flop using NOR gate
T Flip flop using NAND gate

26. D Flip Flop Also Known as Data Flip flop
Can be constructed from RS Flip Flop or JK Flip flop by addition of an inverter.
Inverter is connected so that the R input is always the inverse of S (or J input is always complementary of K).
The D flip flop will act as a storage element for a single binary digit (Bit).

27. D Flip Flop - Symbol

28. D Flip Flop- Logic circuit-Truth Table

29. T Flip Flops and D Flip Flops can be Built using JK Flip Flop
The JK flip flop is considered as a universal flip flop.
A combination of JK flip flop and an inverter can construct a D Flip Flop as shown in Figure.
It also can construct T Flip Flop by combine both J and K inputs with HIGH level input as shown in Figure.

30. Master-Slave Edge-Triggered Flip-Flop
Can connect two level-sensitive latches in Master-Slave configuration to form edge-triggered flip-flop.
Master latch “catches” value of “D” at “QM” when CLK is low.
Slave latch causes “Q” to change only at rising edge of CLK.

31. Master-Slave Edge-Triggered Flip-FlopQM D

32. Master-Slave Edge-Triggered Flip-Flop
Master-Slave configuration
MASTER
SLAVE D Q
CLK
36 Transistors
Compared to transistor version
CLK
CLK D Q
CLK
CLK
8 Transistors