Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-1 Panorama of VLSI Design Fabrication (Chem, physics) Technology (EE) Systems (CS) Matel Science Process Design Device Design Circuit Design Chip Design Single-chip  Proc. Systems Design Properties of Design I, V Speed RAM’s Structured Chip Semiconductor Rules Power Gate Array Logic Sets You are Here! Need for : Global viewpoint Understanding design process Structured method to design Impact on Computer/digital, architecture/system What do you do with over 10M transistors on a chip?

Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-2 Digital Systems Design Trends  Systems on a single IC (chip) Systems designer must understand technology transistors, circuit and logic designs.  New Hardware/Software Tradeoffs New, faster solution in H/W (FP, GX)  New System Design Opportunities Specialized hardware/chips (Video games…)  Push Towards Customized Chips Performance-logic and circuit design Cost-layout, technology  Rapid Prototyping Technologies Chip implementation services Semi-custom design styles  MOS Technology Density & simple structure

Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-3 VLSI Chip Design Process Chip ideas & system spec. Behavioral / functional description (HDL) Structural description (RTL) Logic Design (Gates) Circuit Design (transistors) Layout / Mask (layers) Fabrication Testing & debugging  Understanding VLSI design = understanding each level Reasons for iteration - performance NOT predictable until physical design is complete - testability iterations N bit adder S[]=a[]+b[] a b S +

Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-4 DESIGN FLOW CHART SYSTEM CONCEPT BEHABIOR SIMULATION SYSTEM PARTITION FLOOR PLAN BLOMK DESIGN FULL CUSTOMSEMI-CUSTOMSTANDARD CELL State diagram truth table basic gates transistor sizing PLA generator data path block RAM block ROM block cell libraries counter JK FF MUX SCAN FF LOGIC AND TIMING SIMULATION DESIGN FOR TESTABILITY CHECK

Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-5 (DESIGN FLOW CHART CONTINUE) ATPG/FEST VESTOR GENERATION AUTO PLACEMENT AND ROUTE BACK ANNOTATION AND TIMING CHECK LVS/SWITCH LEVEL SIMULATION DESIGN RULE CHECK GDS II FILE GENERATION MASK SHOP

Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-6 Technology Trends-Microprocessor Year Processor Technology # Transistors Speed (Clock Rate) PMOS 2,  s ( 4b add ) NMOS 29,  s (16b add) NMOS 29,  s (16b add) CMOS 275,  s (32b add) CMOS 1,200,000 40MHz 1992* 586 4,500,000 60MHz 1996* ,000, MHz 2000* M 250MHz 10 4  transistor counts in 25 years ( ) *Projections

Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-7 VLSI Designer’s Job Assemble transistors most effectively to build a system components or an entire system.  Must understand system design goals and system architecture as well as basic technology. (Global View) Design complexity — from managing millions of transistors and their interactions  Must use CAD Tools e.g. Use calculator to calculate complex problems. Use computer to design computers  Time spent must be short (design time)  Must get right answer (functionality)  Precision of answer (quality of design speed, power, reliability, size …)

Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-8 VLSI = Complexity How to deal with complexity  Design Methodology Apply rules and constraints to successive processes of a design as we proceed. Good Calculator  fast and better answer  Divide and Conquer Well known software methodology  -processor Registers ALU Decoders RAM Shifter Adder 1bit adder transistor Masks Structural Hierarchy

Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-9 Abstraction / Hierarchy Top down design Bottom up design  Design Abstraction 1.Adder spec. 2.Block diagram 3.Logic diagram 4.Circuits representation 5.Layout 6.Masks

Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-10 Goal : Understand each level of design abstraction and learn how to design. Focus: Layout & Circuit Design given logic diagram. Global View-point: need to understand logic-level design. Start with lowest level—Layout Think of MOS circuit as though it were a 3-layer PC board. Metal 1 (Blue) Poly (Red) n-diffusion (Green) p-diffusion (Brown) Insulation (oxide) Wires on different levels cross with “No effect” except where RED crosses GREEN or BROWN.

Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-11 When Red crosses Green, An NMOS transistor is created. Behaves like voltage controlled switch SD G N MOS Gate Voltage Switch Stick diagram Red Green Brown S G P MOS D Gate Voltage A A’ A

Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-12 V G =0V (low) V G =5V (high) N N VGVG VGVG VGVG VGVG CMOS Inverter Logic Symbol: In 0 1 out 1 0 Switch Logic: in=0 out in=1 “1” “0” NMOS PMOS NMOS PMOS

Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-13 Stick diagram: Red Green Brown V dd out in GND

Integrated Microsystems Lab. EE372 VLSI SYSTEM DESIGNE. Yoon 1-14 Inverter Layout Vdd GND OutIn M1, Blue Poly, Red Pdiff, Brown PC ndc Ndiff, Green