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1 Copyright  2001 Pao-Ann Hsiung SW HW Module Outline l Introduction l Unified HW/SW Representations l HW/SW Partitioning Techniques l Integrated HW/SW.

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Presentation on theme: "1 Copyright  2001 Pao-Ann Hsiung SW HW Module Outline l Introduction l Unified HW/SW Representations l HW/SW Partitioning Techniques l Integrated HW/SW."— Presentation transcript:

1 1 Copyright  2001 Pao-Ann Hsiung SW HW Module Outline l Introduction l Unified HW/SW Representations l HW/SW Partitioning Techniques l Integrated HW/SW Modeling Methodologies l HW and SW Synthesis Methodologies l Industry Approaches to HW/SW Codesign l Hardware/Software Codesign Research l Summary

2 2 Copyright  2001 Pao-Ann Hsiung SW HW Unified HW/SW Representation l Unified Representation – m A representation of a system that can be used to describe its functionality independent of its implementation in hardware or software m Allows hardware/software partitioning to be delayed until trade-offs can be made m Typically used at a high-level in the design process l Provides a simulation environment after partitioning is done, for both hardware and software designers to use to communicate l Supports cross-fertilization between hardware and software domains

3 3 Copyright  2001 Pao-Ann Hsiung SW HW Current Abstraction Mechanisms in Hardware Systems Abstraction The level of detail contained within the system model l A system can be modeled at m System Level, m Algorithm or Instruction Set Level, m Register-Transfer Level (RTL), m Logic or Gate Level, m Circuit or Schematic Level. l A model can describe a system in the m Behavioral domain, m Structural domain, m Physical domain.

4 4 Copyright  2001 Pao-Ann Hsiung SW HW Abstractions in Modeling: Hardware Systems LevelBehaviorStructurePhysical PMS (System) Communicating Processes Processors Memories Switches (PMS) Cabinets, Cables Instruction Set (Algorithm) Register- Transfer Logic Circuit Input-OutputMemory, Ports Processors Board Floorplan Register Transfers ALUs, Regs, Muxes, Bus ICs Macro Cells Logic Equns.Gates, Flip-flopsStd. cell layout Network Equns.Trans., Connections Transistor layout [McFarland90] Start here Work to here © IEEE 1990

5 5 Copyright  2001 Pao-Ann Hsiung SW HW Current Abstraction Mechanisms for Software Systems Virtual machine A software layer very close to the hardware that hides the hardware’s details and provides an abstract and portable view to the application programmer Attributes m Developer can treat it as the real machine m A convenient set of instructions can be used by developer to model system m Certain design decisions are hidden from the programmer m Operating systems are often viewed as virtual machines

6 6 Copyright  2001 Pao-Ann Hsiung SW HW Abstractions for Software Systems Virtual Machine Hierarchy Application Programs Utility Programs Operating System Monitor Machine Language Microcode Logic Devices

7 7 Copyright  2001 Pao-Ann Hsiung SW HW Abstract Hardware-Software Model Uses a unified representation of system to allow early performance analysis Abstract HW/SW Model General Performance Evaluation of Design Alternatives Evaluation of HW/SW Trade-offs Identification of Bottlenecks

8 8 Copyright  2001 Pao-Ann Hsiung SW HW Examples of Unified HW/SW Representations Systems can be modeled at a high level as: l Data/control flow diagrams l Concurrent processes l Finite state machines l Object-oriented representations l Petri Nets

9 9 Copyright  2001 Pao-Ann Hsiung SW HW Unified Representations (Cont.) l Data/control flow graphs m Graphs contain nodes corresponding to operations in either hardware or software m Often used in high-level hardware synthesis m Can easily model data flow, control steps, and concurrent operations because of its graphical nature Example: + + + + 5 X 4 Y Control Step 1 Control Step 2 Control Step 3

10 10 Copyright  2001 Pao-Ann Hsiung SW HW Unified Representations (Cont.) l Concurrent processes m Interactive processes executing concurrently with other processes in the system-level specification m Enable hardware and software modeling l Finite state machines m Provide a mathematical foundation for verifying system correctness, simulation, hardware/software partitioning, and synthesis m Multiple FSMs that communicate can be used to model reactive real-time systems

11 11 Copyright  2001 Pao-Ann Hsiung SW HW Unified Representations (Cont.) l Object-oriented representations: m Use techniques previously applied to software to manage complexity and change in hardware modeling m Use C++ to describe hardware and display OO characteristics m Use OO concepts such as q Data abstraction q Information hiding q Inheritance m Use building block approach to gain OO benefits q Higher component reuse q Lower design cost q Faster system design process q Increased reliability

12 12 Copyright  2001 Pao-Ann Hsiung SW HW Unified Representations (Cont.) Object-oriented representation Example: 3 Levels of abstraction: Register Read Write ALU Processor Add Sub AND Shift Mult Div Load Store

13 13 Copyright  2001 Pao-Ann Hsiung SW HW Unified Representations (Cont.) l Petri Nets: a system model consisting of places, tokens, transitions, arcs, and a marking m Places - equivalent to conditions and hold tokens m Tokens - represent information flow through system m Transitions - associated with events, a “firing” of a transition indicates that some event has occurred m Marking - a particular placement of tokens within places of a Petri net, representing the state of the net Example: Token Transition Input Places Output Place


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