1. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Arithmetic Building Blocks

2. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic A Generic Digital Processor

3. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Building Blocks for Digital Architectures Arithmetic unit - Bit-sliced datapath ( adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus

4. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Bit-Sliced Design

5. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Full-Adder

6. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic The Binary Adder

7. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Express Sum and Carry as a function of P, G, D

8. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic The Ripple-Carry Adder

9. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Complimentary Static CMOS Full Adder

10. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Inversion Property

11. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Minimize Critical Path by Reducing Inverting Stages

12. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic The better structure: the Mirror Adder

13. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic The Mirror Adder The NMOS and PMOS chains are completely symmetrical. This guarantees identical rising and falling transitions if the NMOS and PMOS devices are properly sized. A maximum of two series transistors can be observed in the carry- generation circuitry. When laying out the cell, the most critical issue is the minimization of the capacitance at node C o. The reduction of the diffusion capacitances is particularly important. The capacitance at node C o is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell. The transistors connected to C i are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.

14. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Quasi-Clocked Adder

15. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic NMOS-Only Pass Transistor Logic

16. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic NP-CMOS Adder

17. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic NP-CMOS Adder A 0 B 0 A 1 B 1 S 0 S 1 C o1 C i0

18. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Manchester Carry Chain

19. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Sizing Manchester Carry Chain

20. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Carry-Bypass Adder

21. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Manchester-Carry Implementation

22. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Carry-Bypass Adder (cont.)

23. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Carry Ripple versus Carry Bypass

24. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Carry-Select Adder

25. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Carry Select Adder: Critical Path

26. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Linear Carry Select

27. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Square Root Carry Select

28. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Adder Delays - Comparison

29. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic LookAhead - Basic Idea

30. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Look-Ahead: Topology

31. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Logarithmic Look-Ahead Adder

32. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Brent-Kung Adder

33. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic The Binary Multiplication

34. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic The Binary Multiplication

35. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic The Array Multiplier

36. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic The MxN Array Multiplier — Critical Path Critical Path 1 & 2

37. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Carry-Save Multiplier

38. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Adder Cells in Array Multiplier

39. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Multiplier Floorplan

40. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Wallace-Tree Multiplier

41. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Multipliers —Summary

42. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Design as a Trade-Off

43. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Layout Strategies for Bit- Sliced Datapaths

44. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Layout of Bit-sliced Datapaths

45. Digital Integrated Circuits© Prentice Hall 1995 Arithmetic Layout of Bit-sliced Datapaths