AIDA FEE64 production report January 2011 Manufacturing Power Supply FEE64 revision A “3 hour test” 19th January 20111.

Slides:

Advertisements

Similar presentations

PC Board Manufacturing Kate McDonnell & Cherelle Bishop CSU GK-12 Summer Planning 2011.

Advertisements

D. Peterson, “Status of the Cornell/Purdue Program” TPC R&D Mini Workshop, Orsay 12-January Status of the Cornell/Purdue Program: first events with.

Plan for MRPC Production Yongjie Sun Center of Particle Science and Technology University of Science and Technology of China.

Uli Schäfer 1 Production and QA issues Design Modules have been designed, with schematic capture and layout, in Mainz (B.Bauss) Cadence design tools, data.

31st July 2008AIDA FEE Report1 AIDA Front end electronics Report July 2008 Progress Virtex5 FPGA choice Milestones for prototype delivery.

Status of the digital readout electronics Mauro Raggi and F. Gonnella LNF Photon Veto WG CERN 13/12/2011.

9th October 2008AIDA FEE progress report P.J.Coleman-Smith 1 AIDA Frontend Electronics progress report. Mezzanine to FEE64 connection. Mezzanine Layout.

Patrick Coleman-Smith CCLRC Daresbury 1 AGATA Digitiser Summary February 2005 Patrick J. Coleman-Smith For the Digitiser Technical Group  I.Lazarus Daresbury.

Project Status. Work Completed IR communication(Protocol, software, and hardware) RF communication(Software and Hardware) Hardware(PCBs) – Pack – Tagger.

21 January 2003Paul Dauncey - UK Electronics1 UK Electronics Status and Issues Paul Dauncey Imperial College London.

Leo Greiner IPHC testing Sensor and infrastructure testing at LBL. Capabilities and Plan.

Printed Circuit Board (PCB) manufacture Learning outcomes: To work effectively, independently and in small groups. To understand the importance of personal.

Tuesday September Cambridge1 GDCC “next replacement of the LDA” Franck GASTALDI.

Saverio Minutoli INFN Genova 1 1 T1 Electronic status Electronics Cards involved: Anode Front End Card Cathode Front End Card Read-Out Control card VFAT.

FEE Electronics progress Mezzanine manufacture progress FEE64 testing and VHDL progress Test mezzanine. Trial mechanical assembly 10th November 2009.

AGATA Pre-processing team report AGATA Week, July 2008.

NEDA collaboration meeting at IFIC Valencia, 3rd-5th November 2010 M. Tripon EXOGAM2 project Digital instrumentation of the EXOGAM detector EXOGAM2 - Overview.

AIDA FEE64 development report August 2010 Progress after Texas CAD work Manufacturing 25th August

12th May 2008AIDA FEE Report1 AIDA Front end electronics Report May 2008 Progress Data compression Plan for prototype delivery.

PHENIX upgrade DAQ Status/ HBD FEM experience (so far) The thoughts on the PHENIX DAQ upgrade –Slow download HBD test experience so far –GTM –FEM readout.

L. Greiner 1IPHC meeting – May 7, 2012 STAR HFT Plans for the next year A short report on HFT/PXL plans for post May 2012 TPC – Time Projection Chamber.

LNL 1 SLOW CONTROLS FOR CMS DRIFT TUBE CHAMBERS M. Bellato, L. Castellani INFN Sezione di Padova.

HBD FEM the block diagram preamp – FEM cable Status Stuffs need to be decided….

11th March 2008AIDA FEE Report1 AIDA Front end electronics Report February 2008.

PXL Cable Options LG 1HFT Hardware Meeting 02/11/2010.

CMS ECAL End Cap Meeting CERN 18 Oct to 22 Oct ECAL End Cap High Voltage and Fibre Optic Monitoring Systems Progress. Progress on High Voltage and.

FEE Electronics progress PCB layout progress VHDL progress in TBU Prototype fixtures FEE64 commissioning A few of the remaining tasks 16th July 2009.

CSC ME1/1 Upgrade Status of Electronics Design Mikhail Matveev Rice University March 28, 2012.

FED Overview VME-FPGA TTCrx BE-FPGA Event Builder Buffers FPGA Configuration Compact Flash Power DC-DC DAQ Interface 12 Front-End Modules x 8 Double-sided.

Acquisition Crate Design BI Technical Board 26 August 2011 Beam Loss Monitoring Section William Vigano’ 26 August

Status of NA62 straw electronics Webs Covers Services Readout.

Monday December DESY1 GDCC news Franck GASTALDI.

PSD upgrade: concept and plans - Why the PSD upgrade is necessary? - Concept and status of the PSD temperature control - Concept of the PSD analog part.

Electronics: Junction Cards, Adapter Card, Purple Card, …. Ron Sidwell, K. Harder, T. Sobering, R. Taylor, E. VonToerne, Kansas State U.

1 Calorimeter electronics Upgrade Outcome of the meeting that took place at LAL on March 9th, 2009 Calorimeter Upgrade Meeting Barcelona March 10th-11st,

Status of the PSD upgrade - Problems with PSD in Be runs - Modification of cooling system - New temperature control - Upgrade of HV control system - MAPD.

How to make a PCB.

ASSEMBLING THE PCB Have the PCB in front of you as shown. Make sure there are no copper tracks showing. This side is called the component side.

FEE Electronics progress Mezzanine layout progress FEE64 progress FEE64 initial testing Test mezzanine. A few of the remaining tasks 2nd October 2009.

FEE Electronics progress PCB layout 18th March 2009.

9/12/2003Ivan Hruska1 First box prototype –Box design in July ‘03 –Box produced during August ’03 Tested last week in few fingers Small changes necessary.

Raw Status Update Chips & Fabrics James Psota M.I.T. Computer Architecture Workshop 9/19/03.

Tracker Week February presented by John Coughlan RAL FED Status FEDv2 Testing Pre-Series Manufacture Final Production.

Julie Prast, Calice Electronics Meeting at LAL, June 2008 Status of the DHCAL DIF Detector InterFace Board Sébastien Cap, Julie Prast, Guillaume Vouters.

WP7&8 Progress Report ITS Plenary meeting, 10 June 2014 LG, PK, VM, JR.

FEE Electronics progress PCB layout progress VHDL progress in TBU Prototype fixture for software 9th June 2009.

Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC Presented by S. Quinton.

Status report Pillar-1: Technology. The “Helmholtz-Cube” Vertically Integrated Detector Technology Replace standard sensor with: 3D and edgeless sensors,

© Hardware & Coffee with PCB design & manufacturing.

PCB Assembly. INTRODUCTION  PCB abbreviation is a printed circuit board,also known as a printed wiring board.  For electronics PCB is used to build.

Outline Upgrade status of the ECAL/HCAL HV control mezzanine board;  Firmware design,  Setup for making functional tests and validation FPGA firmware.

Energy Meters Production & Testing SHIVJI LAL CHOUDHARY.

AIDA: introduction Advanced Implantation Detector Array (AIDA) UK collaboration: University of Edinburgh, University of Liverpool, STFC Daresbury Laboratory.

HE FEE Boards production status 26 th May 2016 Mandakini Patil 1.

SUMMARY OF THE ORSAY LD-TPC ELECTRONICS MEETING

Update on CSC Endcap Muon Port Card

DCH FEE 28 chs DCH prototype FEE &

Status of the DHCAL DIF Detector InterFace Board

Test Slab Status CALICE ECAL test slab: what is it all about?

FEE Electronics progress

Assembly order PCB design

AIDA: introduction Advanced Implantation Detector Array (AIDA)

University of California Los Angeles

FEE Electronics progress

STAR-CBM Joint Workshop Heidelberg, Physikalisches Institut

FEE Electronics progress

LIU BWS Firmware status

Benefits & Advantages of Pogo Pins

Presentation transcript:

AIDA FEE64 production report January 2011 Manufacturing Power Supply FEE64 revision A “3 hour test” 19th January 20111

Manufacturing FEE64: All components purchased and with Jaltek PCB: ExceptionPCB have failed to make the board at the final stage. They put too much copper on the outer layers. The final etch then needs to be longer and this compromises track width of the finer tracks. The board will now be delivered to Jaltek on 24 th January for 10 working day assembly. Mezzanine: Pcbs were delayed from ExceptionPCB due to snow! Assembled boards have questions about the quality of the solder joints. Currently in discussion with Jaltek. Boards returned to Jaltek today for joint x-ray and re-work 19th January 20112

Power Supply One PowerStax system has been purchased by Liverpool. This is being assembled, tested and then used at Daresbury for evaluation and testing the first FEE64 from Jaltek. Liverpool are making a cable using the FEE64 connectors and low loss wire. 8 FEE64 board power system and two cables delivered to Daresbury today. It will be connected to the mezzanine power supply of an existing board to test for any problems in changing resolution. 19th January 20113

FEE64 revision A “3 hour test” Purpose Validate the revision A design prior to full manufacture. The production line will be held for one day and approval must be given by midday. Scope 1.Test the power supplies for correct function and noise. 2.Test the SDRAM, Gbit, PowerPC and Flash memory. 3.If time allows the data links with the FADC devices and the clock distribution will be tested. 4.A Mezzanine, with known performance, will be used to test the new buffer and slow ADCs. Whatif Failure to approve will require a £2000 set-up fee to re-start production. The majority of the components will be saved for a potential new pcb (£14,500). 19th January 20114

FEE64 revision A “3 hour test” Preparation Validating the test firmware using a prototype board and causing faults to check the error reporting. Testing a power system using a blank pcb prior to test with the first boards. Creating the firmware to work with the new ADCs for the ASIC readout. 19th January 20115