Low Power, High-Throughput AD Converters Scan-Flash ADC Low Power, High-Throughput AD Converters Melvin Eze Pennsylvania State University eze@cse.psu.edu Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Outline ADC Converters Flash ADC Scan-Flash Architecture Target Specifications Schedule References Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

Analog-Digital Converters Pre-Processing A/D Conversion DSP D/A Post-Processing Filters ? 000 ..001.. 011 Analog Output Analog Input DSP is really wonderful but… Real World Signals are Analog: Continuous time Continuous amplitude DSP can only process: Discrete time Discrete amplitude Need for data conversion from Analog to Digital and back Slide Adapted from: Haideh Khorramabadi EE247 Class Slides Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

Example: A typical Cell Phone Contains an Integrated form of: 4 Rx Filters 4 Tx Filters 4 Rx ADCs 4 Tx DACs 3 Auxiliary ADCs 8 Auxiliary DACs Slide Adapted from: Haideh Khorramabadi EE247 Class Slides Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Flash ADC Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Flash ADC VIN VREF 5 4.9 4.8 4.7 . 2.5 2.4 0.3 0.2 0.1 0.0 4.75 4.75 5 4.9 4.8 4.7 . 2.5 2.4 0.3 0.2 0.1 0.0 4.75 5 4.75 4.75 Encoding Logic 4.75 4.9 4.7 4.75 4.75 4.75 4.75 4.75 4.75 Ctotal = (2B - 1) * Ccomparator Ctotal = Comparison count * Ccomparator Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Scan-Flash ADC VIN VREF Encoding Logic Key Features Switched Input Multi-cycle latching of Thermometer code Minimum effect on CIN Control Logic is Shift-Register based Implement multi-channel ADCs Other Features Reduces capacitance per comparison Naturally amenable to optimization alg EN EN EN EN EN High frequency clock Switch Control Logic Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Scan-Flash ADC VIN VREF Scan Techniques for B-bit ADC Linear Scan [O(2B)] Very Simple but very inefficient Binary Tree Scan [O(B)] Very efficient but tough to implement so far Linear Window Scan [O(K)] K > B, but be implementation characteristics Encoding Logic EN EN EN EN EN High frequency clock Switch Control Logic Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

Multi channel-Flash ADC VIN_1 VIN_2 VIN_K VREF K stages Encoding Logic EN EN EN EN EN High frequency clock Switch Control Logic Switch Control Logic Switch Control Logic Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

Target Specifications 2 Channels [2-Scan-Flash ADC] 8 bit per channel Power Supply: 5V Power Consumption: 400 mW DNL/INL: 1 LSB Area: 1mm2 Speed: 50 MSPS per channel (100 MSPS aggregate) Operating Frequency: 100MHz Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

Low Power, High-Throughput AD Converters Scan-Flash ADC Low Power, High-Throughput AD Converters Melvin Eze Pennsylvania State University eze@cse.psu.edu Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Schedule Week 1: Specifications and Initial Simulations Week 2: Complete SPICE Implementation of Switch Week 3: Complete Verilog Implementation of Digital Control Week 4: Schematic Layout of single channel SCAN-FLASH -no ROM in Cadence Schematic Editor Week 5: Begin Module layout in Virtuoso and SPICE simulations Week 6: More Layout Week 7: Complete Layout Week 8: Full System test and Performance Analysis Week 9: Debug and Complete Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Progress Week 1 - Week 4 Initial simulation of 3-bit single channel Simulation and schematic layout Initial Floor plan for layout Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Design Verification Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Binary Tree Input Resistors Output Registers Control Registers Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Input Stage Track and Hold T_H sampling clock 1 pF capacitor 100 MHz bandwidth Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Input Stage Track and Hold Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Tree Stage Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Tree Stage Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design V_switch Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Comparator Simulation Data Max Gain-Bandwidth: 6g Open Loop Gain: 200 Power: 17mW Test Voltage: 3.3V Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Comparator Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Output Stage Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Control Registers Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Projected Floorplan Silicon Substrate Comparators Analog Input/VDD T/H blocks Shift Registers Clock Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Components Scan/Hold, Unity Gain, Comparator, Resistor Ladder, D Flip-flop, DC Biasing Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Scan-Flash ADC VIN VREF Scan Techniques for B-bit ADC Linear Scan [O(2B)] Very Simple but very inefficient Binary Tree Scan [O(B)] Very efficient but tough to implement so far Linear Window Scan [O(K)] K > B, but be implementation characteristics Encoding Logic EN EN EN EN EN High frequency clock Switch Control Logic Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Binary Tree Input Resistors Output Registers Control Registers Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Final Design Key Features . Multi-Stage T/H . Two Signal Control . Bussed Stage Output . High Speed, Pipelined Outputs go to registers Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design 8 bit S/F ADC Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Track / Hold Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Unity Gain Buffer Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design T/H Layout  Track/Hold Capacitor with Unity Gain Stage for chaining Approx Max freq: 100MHz Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Multi Stage T/H 8 stage T/H chain for 8-bit ADC Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Design Details Cell Tree Design Features . No Resistor Ladder! . No Thermometer code! . Max Freq determined by timing on last stage Output Register Features . No Wide OR gates! . Only control: CLOCK . No Decoder Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Cell Module Schematic Design becomes very modular! Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design D Latch Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design D flip Flop Simple Master-Slave configuration Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design D Flip Flop Layout Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Comparator Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Cell Layout Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design 8 bit S/F ADC Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design 3-bitADC Layout Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design

CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design References Rezhavi, B: CMOS Analog Circuit Design Spring 2006 CSE 598A: Analog-Digital Mixed-Signal CMOS Chip Design