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Real time DSP Professors: Eng. Julian S. Bruno Eng. Jerónimo F. Atencio Sr. Lucio Martinez.

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Presentation on theme: "Real time DSP Professors: Eng. Julian S. Bruno Eng. Jerónimo F. Atencio Sr. Lucio Martinez."— Presentation transcript:

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2 Real time DSP Professors: Eng. Julian S. Bruno Eng. Jerónimo F. Atencio Sr. Lucio Martinez

3 Analog to digital Converter

4 The BIG picture Real time algorithms Results FAST!

5 Signals  Amplitude  Frequency  Noise

6 Continuous Signal

7 External Noise

8 Quantization Noise Analog Input range: Vin = 0 to FS (Full Scale) Resolution: N = 3 bits Code: 2 N = 8 Full Scale = 10V Voltage step or quantum (Q = FS/N)

9 Unipolar Binary Codes ScaleFS (10V)Binary 7/88,75111 3/47,5110 5/86,25101 1/25100 3/83,75011 1/42,5010 1/81,25001 00000

10 Bipolar Binary Codes ScaleFS (+/-5V)Two Comp. 3/43,75011 1/22,5010 1/41,25001 00000 - 1/4-1,25111 - 1/2-2,5110 - 3/4-3,75101 -5100

11 Errors in a data converter

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13 Quantization noise

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17 Noise Floor AD7722

18 Noise Floor

19 Cuantización uniforme

20 Cuantización no uniforme

21 A-law

22 Tabla de codificación

23 Companding

24 Expansion

25 Differences Between A−Law and u−Law

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27 Basic ADC Analog: Analog Input Reference Voltage Analog Ground Analog Power Supply Digital: Digital output Control Signals Sampling Clock Digital Ground Digital Power Supply

28 1-Bit DAC

29 Flash converters Expensives High power Resolution limited to around 8-bits Large chip size Fast Resistors: 2 N Comparators: 2 (N-1)

30 Flash converters

31 SAR The accuracy and linearity is determined by the DAC Available in resolutions up to 16-bits

32 SAR

33 Delta Modulation

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35 First-Order Sigma-Delta ADC

36 Analysis of Sigma-Delta Modulator The integrator acts as a lowpass filter to the input signal and a highpass filter to the quantization noise

37 Oversampling

38 Second-Order Sigma-Delta ADC

39 Architecture tradeoffs


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